Method and apparatus for updating flash memory resident firmware through a standard disk drive interface

• US 6,009,497 A
• Filed: 11/09/1998
• Issued: 12/28/1999
• Est. Priority Date: 02/19/1993
• Status: Expired due to Term

• Current Assignee: Intel Corporation
• Original Assignee: Intel Corporation
• Inventors: Garner, Richard, Wells, Steven E., Kendall, Terry L., Brown, Dave M., Kynett, Virgil Niles
• Primary Examiner(s): Cabeca, John W.
• Assistant Examiner(s): Tran, Denise
• Application Number:
  US09/189,000
• Time in Patent Office: 414 Days
• Field of Search: 711/102-104, 371/10.2, 371/21.1, 365/185.22, 365/185.29, 365/185.33, 365/218, 365/185.01, 365/94, 712/32, 712/37, 714/710, 714/718
• US Class Current: 711/103
• CPC Class Codes: G06F 3/0607 by facilitating the process of upgrading existing storage systems, e.g. for improving compatibility between host and storage device
• CPC Class Codes: G06F 3/0632 by initialisation or re-initialisation of storage systems
• CPC Class Codes: G06F 3/0676 Magnetic disk device
• CPC Class Codes: G06F 8/65 Updates security arrangements therefor G06F21/57

Abstract

A method for updating the content of EEPROM memory used for controlling processes run on a microprocessor used to control the operations of a long term memory array which includes moving an update process stored in the EEPROM memory to a random access memory associated with the microprocessor; and then using the update process stored in random access memory for erasing the contents of the EEPROM memory, and furnishing data to the microprocessor on a sector by sector basis from a host computer through an interface used by the microprocessor to provide data to the long term memory array. The data furnished by the host is written sector by sector to the EEPROM memory until the EEPROM memory has been updated.

Claims

1. An apparatus comprising:

a microprocessor to execute a plurality of processes for controlling operations of a long term memory array;

an EEPROM memory, coupled to the microprocessor, to store the plurality of processes; and

a random access memory, coupled to the microprocessor, to store one or more of the plurality of processes for execution by the microprocessor;

the microprocessor, in response to an update command from a host processor, to write an update process stored in the EEPROM memory to the random access memory and execute the update process to erase the EEPROM memory, receive a predetermined amount of data from the host processor through a standard disk drive interface, wherein the host processor provides other data to the long term memory array via the standard disk drive interface as if the long term memory array were a standard disk drive, the microprocessor further to write the predetermined amount of data to the EEPROM memory, and continue receiving and writing the predetermined amount of data until the EEPROM memory has been updated, the microprocessor and the host processor to reset after the EEPROM memory has been updated.

2. The apparatus of claim 1 wherein the predetermined amount of data comprises a sector of data.

3. The apparatus of claim 1 further comprising a buffer to receive the predetermined amount of data from the host processor, the microprocessor to write the predetermined amount of data from the buffer to the EEPROM.

4. The apparatus of claim 1 wherein the microprocessor, in response to the update command from the host processor, is further to write all processes used by the update process stored in the EEPROM memory to the random access memory.

5. The apparatus of claim 1 wherein the microprocessor is further to execute the update process to verify successful erasure of the EEPROM memory, and write the predetermined amount of data to the microprocessor only if erasure of the EEPROM memory was successful.

6. An apparatus for updating an EEPROM memory which stores processes run on a microprocessor used to control operations of a long term memory array, the apparatus comprising:

means for writing, in response to an update command of a host processor, an update process stored in the EEPROM memory to a random access memory associated with the microprocessor; and

means for using the update process stored in random access memory, said means for using comprising

means for erasing the EEPROM memory,

means for furnishing a predetermined amount of data to the microprocessor from a host processor through a standard disk drive interface, wherein the host processor provides other data to the long term memory array via the standard disk drive interface as if the long term memory array were a standard disk drive,

means for writing the predetermined amount of data to the EEPROM memory,

the means for furnishing and means for writing continuing the furnishing and the writing until the EEPROM memory has been updated, and

means for resetting the microprocessor and the host processor after the EEPROM memory has been updated.

7. The apparatus of claim 6 wherein the predetermined amount of data comprises a sector of data.

8. The apparatus of claim 6 further comprising:

means for buffering the predetermined amount of data received from the host processor, the means for writing the predetermined amount of data to the EEPROM memory comprises means for writing the predetermined amount of data from the means for buffering to the EEPROM memory.

9. The apparatus of claim 6 wherein the means for writing the update process further comprising:

means for writing all processes stored in the EEPROM memory used by the update process to the random access memory associated with the microprocessor.

10. The apparatus of claim 6 wherein the means for using the update process further comprises:

means for verifying successful erasure of the EEPROM; and

means for furnishing the predetermined amount of data to the microprocessor only if erasure of the EEPROM was successful.

11. A system comprising:

a host processor; and

a long term memory coupled to the host processor, the long term memory comprising

a microprocessor to execute a plurality of processes for controlling operations of the long term memory array;

an EEPROM memory, coupled to the microprocessor, to store the plurality of processes; and

a random access memory, coupled to the microprocessor, to store one or more of the plurality of processes for execution by the microprocessor;

the microprocessor, in response to an update command from the host processor, to write an update process stored in the EEPROM memory to the random access memory and execute the update process to erase the EEPROM memory, receive a predetermined amount of data from the host processor through a standard disk drive interface, wherein the host processor provides other data to the long term memory array via the standard disk drive interface as if the long term memory array were a standard disk drive, the microprocessor further to write the predetermined amount of data to the EEPROM memory, and continue receiving and writing the predetermined amount of data until the EEPROM memory has been updated, the microprocessor and the host processor to reset after the EEPROM memory has been updated.

12. The system of claim 11 wherein the predetermined amount of data comprises a sector of data.

13. The system of claim 11, the long term memory array further comprising a buffer to receive the predetermined amount of data from the host processor, the microprocessor to write the predetermined amount of data from the buffer to the EEPROM.

14. The system of claim 11 wherein the microprocessor, in response to the update command from the host processor, is further to write all processes used by the update process stored in the EEPROM memory to the random access memory.

15. The system of claim 11 wherein the microprocessor is further to execute the update process to verify successful erasure of the EEPROM memory, and write the predetermined amount of data to the microprocessor only if erasure of the EEPROM memory was successful.