Transition analysis and circuit resynthesis method and device for digital circuit modeling

• US 6,009,531 A
• Filed: 05/27/1997
• Issued: 12/28/1999
• Est. Priority Date: 08/10/1995
• Status: Expired due to Term

• Current Assignee: Mentor Graphics Corporation (Siemens AG)
• Original Assignee: IKOS Systems Incorporated (Siemens AG)
• Inventors: Dahl, Matthew L., Selvidge, Charles W.
• Primary Examiner(s): Heckler, Thomas M.
• Application Number:
  US08/863,963
• Time in Patent Office: 945 Days
• Field of Search: 713/400, 710/8, 710/10, 710/12, 712/10, 712/15, 712/36, 712/37
• US Class Current: 713/400
• CPC Class Codes: G06F 1/04 Generating or distributing clock signals or signals derived directly therefrom
• CPC Class Codes: G06F 1/10 Distribution of clock signals , e.g. skew
• CPC Class Codes: G06F 30/331 with hardware acceleration, e.g. by using field programmable gate array [FPGA] or emulation
• CPC Class Codes: G06F 30/34 for reconfigurable circuits, e.g. field programmable gate arrays [FPGA] or programmable logic devices [PLD]

Abstract

A method of configuring a configurable logic system, including a single or multi-FPGA network, is disclosed in which an internal clock signal is defined that has a higher frequency than timing signals the system receives from the environment in which it is operating. The frequency can be at least ten times higher than a frequency of the environmental timing signals. The logic system is configured to have a controller that coordinates operation of its logic operation in response to the internal clock signal and environmental timing signals. Specifically, the controller is a finite state machine that provides control signals to sequential logic elements such as flip-flops. The logic elements are clocked by the internal clock signal. In the past, emulation or simulation devices, for example, operated in response to timing signals from the environment. A new internal clock signal, invisible to the environment, rather than the timing signals is used to control the internal operations of the devices. Additionally, a specific set of transformations are disclosed that enable the conversion of a digital circuit design with an arbitrary clocking methodology into a single clock synchronous circuit.

Claims

1. A method of configuring a configurable logic system to operate in an environment, the logic system generating output signals to the environment in response to at least one environmental timing signal and environmental data signals provided from the environment, the method comprising:

configuring the logic system to perform logic operations for generating the output signals in response to the environmental data signals and an internal clock signal; and

configuring the logic system to comprise a finite state machine for generating control signals to control the logic operations in response to the environmental timing signal and the internal clock signal.

2. A method of configuring as described in claim 1, further comprising configuring the logic system to comprise a synchronizer for sampling the environmental timing signal in response to the internal clock signal.

3. A method of configuring as described in claim 1, wherein the logic system comprises at least one field programmable gate array.

4. A method of configuring as described in claim 1, further comprising configuring the finite stare machine to dictate set-up and hold times of signals to the environment.

5. A method of configuring as described in claim 1, further comprising configuring the finite state machine to dictate sampling times of the environmental data signals.

6. A method of configuring as described in claim 1, further comprising configuring the logic system to have combinational logic and sequential logic to perform the logic operations.

7. A method of configuring as described in claim 6, further comprising configuring the finite state machine to generate control signals to the sequential logic in response to the environmental timing signal and the internal clock signal.

8. A method of configuring as described in claim 7, further comprising configuring the sequential logic to comprise flip-flops receiving the internal clock signal at a clock input and the control signals at a latch enable input.

9. A method of configuring as described in claim 1, wherein the logic system comprises a plurality of configurable logic devices electrically connected via an interconnect for transmitting signals between the chips.

10. A method of configuring as described in claim 9, wherein the interconnect comprises cross bar chips.

11. A method as configuring as described in claim 9, wherein the interconnect utilizes a direct-connect topology.

12. A method of configuring as described in claim 11, wherein the interconnect includes buses.

13. A logic system for generating output signals to an environment in response to at least one environmental timing signal and environmental data signals provided from the environment, the logic system comprising:

an internal clock for generating an internal clock signal for the logic system;

at least one configurable logic device including;

logic which generates the output signals in response to the environmental data signals and the internal clock signal; and

a finite state machine which coordinates operation of the logic in response to the internal clock signal and the environmental timing signal.

14. A logic system as described in claim 13, wherein the at least one configurable logic device comprises at least one field programmable gate array.

15. A logic system as described in claim 13, further comprising an interconnect for transmitting signals between plural configurable logic devices.

16. A logic system as described in claim 13, further comprising a synchronizer for sampling the environmental timing signal in response to the internal clock signal.

17. A logic system as described in claim 16, wherein the synchronizer is constructed from non-programmable logic.

18. A logic system as described in claim 13, wherein the logic comprises combinational logic and sequential logic.

19. A logic system as described in claim 18, wherein the sequential logic comprises flip-flops receiving the internal clock signal at a clock input and the control signals at a latch enable input.