Ball grid array semiconductor package with solder ball openings in an insulative base

• US 6,011,694 A
• Filed: 08/01/1997
• Issued: 01/04/2000
• Est. Priority Date: 08/01/1996
• Status: Expired due to Fees

• Current Assignee: Fuji Machinery Mfg. & Electronics Co., Ltd. (Kyoden Company Limited)
• Original Assignee: Fuji Machinery Mfg. & Electronics Co., Ltd. (Kyoden Company Limited)
• Inventors: Hirakawa, Tadashi
• Primary Examiner(s): SPARKS, DONALD ALAN
• Application Number:
  US08/904,394
• Time in Patent Office: 886 Days
• Field of Search: 174/16.3, 174/252, 174/255, 174/260, 174/26, 174/263, 174/264, 174/265, 174/266, 174/268, 228/180.21, 228/180.22, 257/692, 257/678, 257/697, 257/698, 257/700, 257/707, 257/712, 257/713, 257/717, 257/723, 257/724, 257/728, 257/737, 257/738, 257/772, 257/778, 257/780, 257/784, 257/786, 361/760, 361/761, 361/763, 361/764, 361/772, 361/774, 361/777, 361/779, 361/783, 361/807, 361/809, 361/813, 438/612, 438/613, 439/68, 439/83, 439/526
• US Class Current: 361/774
• CPC Class Codes: H01L 2224/0401 Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
• CPC Class Codes: H01L 2224/0603 Bonding areas having different sizes, e.g. different heights or widths
• CPC Class Codes: H01L 2224/13099 Material
• CPC Class Codes: H01L 2224/1403 Bump connectors having different sizes, e.g. different diameters, heights or widths
• CPC Class Codes: H01L 2224/16225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/16237 the bump connector connecting to a bonding area disposed in a recess of the surface of the item
• CPC Class Codes: H01L 2224/45144 Gold (Au) as principal constituent
• CPC Class Codes: H01L 2224/48091 Arched
• CPC Class Codes: H01L 2224/48227 connecting the wire to a bond pad of the item
• CPC Class Codes: H01L 2224/48228 the bond pad being disposed in a recess of the surface of the item
• CPC Class Codes: H01L 2224/48465 the other connecting portion not on the bonding area being a wedge bond, i.e. ball-to-wedge, regular stitch
• CPC Class Codes: H01L 2224/49109 outside the semiconductor or solid-state body
• CPC Class Codes: H01L 23/3128 the substrate having spherical bumps for external connection
• CPC Class Codes: H01L 23/36 Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks H01L23/28, H01L23/40, H01L23/42, H01L23/44, H01L23/46 take precedence; heating H01L23/345
• CPC Class Codes: H01L 23/49816 Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
• CPC Class Codes: H01L 24/17 of a plurality of bump connectors
• CPC Class Codes: H01L 24/45 of an individual wire connector
• CPC Class Codes: H01L 24/48 of an individual wire connector
• CPC Class Codes: H01L 24/49 of a plurality of wire connectors
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00012 : Relevant to the scope of the group, the symbol of which is combined with the symbol of this group
• CPC Class Codes: H01L 2924/00014 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01006 : Carbon [C]
• CPC Class Codes: H01L 2924/01027 : Cobalt [Co]
• CPC Class Codes: H01L 2924/01029 : Copper [Cu]
• CPC Class Codes: H01L 2924/01078 : Platinum [Pt]
• CPC Class Codes: H01L 2924/01079 : Gold [Au]
• CPC Class Codes: H01L 2924/014 : Solder alloys
• CPC Class Codes: H01L 2924/12042 : LASER
• CPC Class Codes: H01L 2924/15311 : being a ball array, e.g. BGA
• CPC Class Codes: H01L 2924/1532 : the connection portion being formed on the die mounting surface of the substrate
• CPC Class Codes: H01L 2924/181 : Encapsulation

Abstract

An area grid array package such as a ball grid array enables high pin count and high density with no problems of routing, and at low cost. Independent and non-connected circuits are formed on a first surface and a second surface of an insulative base material, each circuit on each surface having first chip connection pads formed on one end to connect to a semiconductor chip, the other end having second solder ball pads to mount solder balls. The chip is connected to the first connection pads by either bonding wires or connection bumps extending through holes in the base material and are molded by a resin. Each solder ball pad on each surface has a solder ball attached with the solder balls extending through openings in the base material. The insulative base material and the semiconductor chip may be attached to a heat slug.

Claims

1. An area grid array package including independent and non-connected circuits formed on a first surface and a second surface of an insulative base material;

respectively, each circuit on each surface having first pads formed on one end for connection to a semiconductor chip, another end of each circuit having solder ball pads to mount solder balls, each circuit being in electrical connection to a mounted semiconductor chip and the first pads, said circuits and said first pads being molded by an encapsulating resin, each solder ball pad on each surface having a solder ball attached thereto; and

wherein conductive bumps connect the semiconductor chip to the first pads and the solder balls are connected to the solder ball pads, and wherein the diameter of the bumps to be attached to the first pads on the second surface of the insulative base is larger than that of the bumps to be attached to the first pads on the first surface of the insulative base, in order to compensate for the thickness of the insulative base material.

4. The area grid array package of claim 1 wherein the insulative base material and the semiconductor chip are attached to a heat slug.

5. The area grid array package of claim 1 in which the second openings for connecting to the semiconductor chip are formed from the first surface so that the openings reach to the first pads on the second surface.

6. The area grid array package of claim 1 in which the first and second openings are laser-formed openings.

7. The area gird array package of claim 1 in which the insulative base material is a rigid panel.

8. The area grid array package of claim 1 in which the insulative base material is a flexible film or a tape.

9. The area grid array package of claim 1 in which the openings leading to the solder ball pads are filled by a conductive filler to compensate for the thickness of the insulative base material.

10. The area grid array package of claim 1 in which the openings leading to the first pads are filled by a conductive filler to compensate for the thickness of the base material.

11. The area grid array package of claim 10 in which the conductive filler is a conductive resin.

2. An area grid array package including independent and non-connected circuits formed on a first surface and a second surface of an insulative base material;

respectively, each circuit on each surface having first pads formed on one end for connection to a semiconductor chip, another end of each circuit having solder ball pads to mount solder balls, each circuit being in electrical connection to a mounted semiconductor chip and the first pads, said circuits and said first pads being molded by an encapsulating resin, each solder ball pad on each surface having a solder ball attached thereto;

wherein first openings for attaching the solder balls are formed in said insulative base material extending from the second surface and, in which the first openings are filled by a conductive filler to compensate for the thickness of the insulative base material; and

in which the conductive filler is a conductive resin or a plating layer.

3. An area grid array package including independent and non-connected circuits formed on a first surface and a second surface opposite to the first surface of an insulative base material, respectively, each circuit on each surface having first pads formed on one end for connection to a semiconductor chip, another end of each circuit having solder balls pads to mount solder balls, each circuit being in electrical connection to a mounted semiconductor chip and the first pads, said circuits and said first pads being molded by an encapsulating resin, each solder ball pad on each surface having a solder ball attached thereto;

wherein first openings for attaching the solder balls are formed in said insulative base material extending from the second surface such that each opening reaches to one of the solder ball pads, and wherein second openings are formed in the insulative base material for connecting the semiconductor chip to the first pads on the second surface of the insulative base material; and

in which the diameter of the solder balls attached to the pads on the first surface of the insulative base material is larger than that of the solder balls to be attached to the pads on the second surface of the insulative base material to compensate for the thickness of the base material.

12. A ball grid array semiconductor package comprising:

an insulative base material;

circuitry metallizations formed on a first surface and a second surface of the insulative base material the second surface being opposite to the first surface, each circuitry metallization having a first connection pad adjacent one end and a second bonding pad adjacent a second end;

a semiconductor chip mounted adjacent to said first surface and said first connection pads, said chip being electrically connected to said first connection pads of the circuitry metallizations;

wherein the insulative base material has first openings extending from the second surface of the insulative base material at a location under second bonding pads;

wherein each of said first openings confines a portion of a solder ball which is in a solder melt-fixed connection to a facing side of each said second bonding pads, wherein said first openings are in the second surface of the insulative base material and said second openings are either the first or the second surfaces of the insulative base material; and

wherein said second openings are in the first surface and wherein solder balls extend from said chip to connection pads on the first surface and through said second openings to connection pads on said second surface.

13. The ball grid array semiconductor package as defined in claim 12 wherein the insulative base material is a film or a sheet.

14. The ball grid array semiconductor package as defined in claim 12 wherein the insulative base material is a reinforced laminate.

15. The ball grid array package as defined in claim 12 wherein said insulative base material and said chip are adhesively mounted to a heat slug.

16. The ball grid array package as defined in claim 12 wherein a conductive filler is included within said first openings.

17. An area grid array package including independent and non-connected circuits formed on a first surface and a second surface of an insulative base material;

respectively, each circuit on each surface having first pads formed on one end for connection to a semiconductor chip, another end of each circuit having solder ball pads to mount solder balls, each circuit being in electrical connection to a mounted semiconductor chip and the first pads, said circuits and said first pads being molded by an encapsulating resin, each solder ball pad on each surface having a solder ball attached thereto;

wherein the diameter of the solder balls attached to the pads on the first surface of the insulative base material is larger than the diameter of the solder balls to be attached to the pads on the second surface of the insulative base material to compensate for the thickness of the base material; and

wherein a correspondingly large diameter opening is provided in the insulative base material to confine the larger diameter solder balls.

18. An area grid array package including independent and non-connected circuits formed on a first surface and a second surface opposite to the first surface of an insulative base material, respectively, each circuit on each surface having first pads formed on one end for connection to a semiconductor chip, another end of each circuit having solder balls pads to mount solder balls, each circuit being in electrical connection to a mounted semiconductor chip and the first pads, said circuits and said first pads being molded by an encapsulating resin, each solder ball pad on each surface having a solder ball attached thereto;

wherein first openings for attaching the solder balls are formed in said insulative base material extending from the second surface such that each opening reaches to one of the solder ball pads, and wherein second openings are formed in the insulative base material for connecting the semiconductor chip to the first pads on the second surface of the insulative base material; and

in which the opening leading to the first pads is filled with a conductive filler to compensate for the thickness of the base material and the conductive filler is a conductive resin.

19. The area grid array package of claim 18 wherein conductive bumps connect the semiconductor chip to the first pads and the solder balls are connected to the solder ball pads, and wherein the diameter of the bumps to be attached to the first pads on the second surface of the insulative base is larger than that of the bumps to be attached to the first pads on the first surface of the insulative base, in order to compensate for the thickness of the insulative base material.