Printed circuit substrate with solder formed on pad-on-via and pad-off-via contacts thereof

• US 6,020,561 A
• Filed: 11/12/1996
• Issued: 02/01/2000
• Est. Priority Date: 03/29/1996
• Status: Expired due to Term

• Current Assignee: Intel Corporation
• Original Assignee: Intel Corporation
• Inventors: Ichikawa, Kinya, Ishida, Kenzo, Mashimoto, Yohko
• Primary Examiner(s): Kincaid, Kristine
• Assistant Examiner(s): Cuneo, Kamand
• Application Number:
  US08/745,470
• Time in Patent Office: 1,176 Days
• Field of Search: 174/261, 174/262, 174/263, 174/260, 361/774, 361/777, 361/779, 257/737, 257/738, 257/723, 257/724, 257/780, 257/778, 228/180.22, 438/612, 438/613
• US Class Current: 174/261
• CPC Class Codes: H01L 21/4853 Connection or disconnection of other leads to or from a metallisation, e.g. pins, wires, bumps
• CPC Class Codes: H01L 2224/0231 Manufacturing methods of the redistribution layers
• CPC Class Codes: H01L 2224/0401 Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
• CPC Class Codes: H01L 2224/0603 Bonding areas having different sizes, e.g. different heights or widths
• CPC Class Codes: H01L 2224/13099 Material
• CPC Class Codes: H01L 2224/13111 Tin [Sn] as principal constituent
• CPC Class Codes: H01L 2224/1403 Bump connectors having different sizes, e.g. different diameters, heights or widths
• CPC Class Codes: H01L 2224/81801 Soldering or alloying
• CPC Class Codes: H01L 23/49811 Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads H01L23/49827 takes precedence
• CPC Class Codes: H01L 23/49894 Materials of the insulating layers or coatings
• CPC Class Codes: H01L 24/14 of a plurality of bump connectors
• CPC Class Codes: H01L 24/81 using a bump connector
• CPC Class Codes: H01L 2924/01005 Boron [B]
• CPC Class Codes: H01L 2924/01006 Carbon [C]
• CPC Class Codes: H01L 2924/01029 Copper [Cu]
• CPC Class Codes: H01L 2924/01033 Arsenic [As]
• CPC Class Codes: H01L 2924/0105 Tin [Sn]
• CPC Class Codes: H01L 2924/01082 Lead [Pb]
• CPC Class Codes: H01L 2924/014 Solder alloys
• CPC Class Codes: H01L 2924/14 Integrated circuits
• CPC Class Codes: H05K 1/114 : Pad being close to via, but not surrounding the via
• CPC Class Codes: H05K 2201/09472 : Recessed pad for surface mounting recess in pad H05K2201/09745; Recessed electrode of component
• CPC Class Codes: H05K 2201/10674 : Flip chip
• CPC Class Codes: H05K 2203/043 : Reflowing of solder coated conductors, not during connection of components, e.g. reflowing solder paste
• CPC Class Codes: H05K 3/1216 : by screen printing or stencil printing
• CPC Class Codes: H05K 3/3485 : Applying solder paste, slurry or powder thick film methods for applying conductive paste or ink patterns H05K3/12

Abstract

A printed circuit substrate having solder bumps formed on pad-on-via contacts and pad-off-via contacts. The printed circuit substrate has at least one pad-on-via contact and at least one pad-off-via contact. A first solder bump is on the pad-on-via contact and a second solder bump is on the pad-off-via contact. The first and second solder bumps are substantially the same height as measured above a horizontal plane that is substantially co-planar to the pad-off-via contact.

Claims

1. A printed circuit substrate, comprising:

a multilayer substrate;

at least one pad-on-via contact on the multilayer substrate;

at least one pad-off-via contact on the multilayer substrate, wherein said pad-on-via contact is at a lower height from the bottom of the substrate than said pad-off-via contact;

a first solder bump formed on said pad-on-via contact, said first solder bump having a first exposed surface on a side thereof opposing said pad-on-via contact; and

a second solder bump formed on said pad-off-via contact, said second solder bump having a second exposed surface on a side thereof opposing said pad-off-via contact, the first and second exposed surfaces being at substantially the same height from the bottom of the substrate so as to be capable of establishing a solder connection with an electronic device having contacts at the same height.

2. The printed circuit substrate of claim 1 wherein said solder comprises 97/3 Pb/Sn.

3. The printed circuit substrate of claim 1 wherein said pad-on-via contact has a depth of approximately 50-70 microns.

4. The printed circuit substrate of claim 1 wherein said pad-off-via contact has a depth of approximately 10-30 microns.