Core cell structure and corresponding process for NAND-type high performance flash memory device

CAFC
  • US 6,023,085 A
  • Filed: 12/18/1997
  • Issued: 02/08/2000
  • Est. Priority Date: 12/18/1997
  • Status: Expired due to Term
First Claim
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1. A NAND-type flash memory device, comprising:

  • a core region comprising a stacked gate flash memory cell structure and a select gate transistor; and

    a periphery region comprising a low voltage transistor and a high voltage transistor, wherein the select gate transistor and the low voltage transistor both have a gate oxide layer and a gate electrode layer,wherein a thickness of the gate oxide layer of the select gate transistor and the low voltage transistor are substantially the same, and a thickness of the gate electrode layer of the select gate transistor and the low voltage transistor are substantially the same.

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