Signal delays in a logical repeater set

• US 6,023,476 A
• Filed: 01/31/1997
• Issued: 02/08/2000
• Est. Priority Date: 01/31/1997
• Status: Expired due to Term

• Current Assignee: Advanced Micro Devices, Inc.
• Original Assignee: Advanced Micro Devices, Inc.
• Inventors: Lo, William
• Primary Examiner(s): NGO, RICKY QUOC
• Application Number:
  US08/791,180
• Time in Patent Office: 1,103 Days
• Field of Search: 370/274, 370/401, 370/445, 370/447, 370/448, 370/492, 370/501, 370/502, 370/517, 370/252, 370/461, 370/462, 370/402, 370/463, 375/221, 375/211, 375/212
• US Class Current: 370/502
• CPC Class Codes: H04L 12/44 Star or tree networks

Abstract

A logical repeater set provides for delaying a character of data that passes through the logical repeater set from a receive channel in a receiving repeater set to a set of transmit channels in transmitting repeater sets. In providing for the delay of a character, the receiving repeater set calculates a receive channel character delay value, and receives a character that is to be provided on a transmit channel. The receiving repeater set then delays the character for a period of time equal to the receive channel character delay value and providing the character to the transmitting repeater set. Each transmitting repeater set further calculates a set of transmit channel character delay values for a set of transceivers. Each transmitting repeater set receives a character from the receiving repeater set that is to be provided on a transmit channel and further delays the character by a transmit channel character delay value. A receiving repeater set and transmitting repeater set may be either the same repeater set or a pair of repeater sets that are coupled together via an expansion bus.

Claims

1. A method for delaying a character in a logical repeater set, said method comprising the steps of:

(a) receiving said character in a receiving repeater set;

(b) determining a receive channel character delay value in said receiving repeater set in response to receiving said character;

(c) delaying said character for a period of time equal to said receive channel character delay value;

(d) providing said character to a transmitting repeater set;

(e) determining a transmit channel character delay value in response to said character being provided in step (d);

(f) delaying said character for a period of time equal to said transmit channel character delay value; and

(g) providing said character to a transmit channel of a transceiver in the transmitting repeater set.

2. The method of claim 1, wherein said step (b) includes determining a receive bit delay value by performing the following calculation:

##EQU1## wherein;

RBDV is said receive bit delay value for a receiving repeater set in the logical repeater set,

MAX_-- EOJ_-- R is a value equal to or greater than a largest cessation-of-collision JAM (EOJ) propagation delay value for a receive channel of any transceiver (EOJ(rx)) in the logical repeater set,

SOP(rx) is a value substantially equal to a start-of-packet (SOP) propagation delay value of a receive channel of a transceiver (SOP(rx)) in said receiving repeater set that is providing information to the receiving repeater set,

SOP(A) is an arbiter time delay for the logical repeater set,

EOJ(rc) is a value substantially equal to a EOJ value of a repeater unit and an expansion port in the receiving repeater set, and

SOP(rc) is a value substantially equal to a SOP value of a repeater unit and an expansion port in the receiving repeater set.

3. The method of claim 2, wherein said step (b) further includes connecting the receive bit delay value into the receive channel character delay value using the following calculation:

##EQU2## wherein;

RCDV is said receive channel character delay value,

B is a number of bits in said character,

INT[RBDV/B] is equal to a quotient of RBDV divided by B, if the quotient is an integer, else INT[RBDV/B] is equal to an integer portion of the quotient plus 1, and

Q is a maximum allowable number of delay periods.

4. The method of claim 2, wherein said step (b) further includes converting the receive bit delay value into the receive channel character delay value using the following calculation:

space="preserve" listing-type="equation">RCDV=INT[RBDV/B]

wherein;

RCDV is said receive channel character delay value,

B is a number of bits in said character, and

INT[RBDV/B] is equal to a quotient of RBDV divided by B, if the quotient is an integer, else INT[RBDV/B] is equal to an integer portion of the quotient plus 1.

5. The method of claim 1, wherein the receiving repeater set and the transmitting repeater set are both provided using one repeater set.

6. The method of claim 1, wherein step (e) includes determining a transmit channel bit delay value by performing the following calculation:

##EQU3## wherein;

TBDV is said transmit channel bit delay value for a port in a transmitting repeater set in the logical repeater set,

MAX_-- EOJ_-- T is a value equal to or greater than a largest EOJ value for a transmit channel of any transceiver (EOJ(tx)) in the logical repeater set,

SOP(tx) is a value substantially equal to a SOP value of a transmit channel of a transceiver in said transmitting repeater set for which TBDV is being calculated,

EOJ(tc) is a value substantially equal to an EOJ value of a repeater unit and an expansion port in the transmitting repeater set, and

SOP(rc) is a value substantially equal to a SOP value of a repeater unit and an expansion port in the transmitting repeater set.

7. The method of claim 6, wherein step (e) further includes using the transmit channel bit delay value to calculate the transmit channel character delay value using the following calculation:

##EQU4## wherein;

TCDV is said transmit channel character delay value;

B is a number of bits in said character,

INT[TBDV/B] is equal to a quotient of TBDV divided by B, if the quotient is an integer, else INT[TBDV/B] is equal to an integer portion of the quotient plus 1, and

Q is a maximum allowable number of delay periods.

8. The method of claim 6, wherein step (e) further includes using the transmit channel bit delay value to calculate the transmit channel character delay value using the following calculation:

space="preserve" listing-type="equation">TCDV=INT[TBDV/B]

wherein;

TCDV is said transmit channel character delay value,

B is a number of bits in said character, and

INT[TBDV/B] is equal to a quotient of TBDV divided by B, if the quotient is an integer, else INT[TBDV/B] is equal to an integer portion of the quotient plus 1.

9. The method of claim 1, wherein said step (a) includes the step of:

indicating that a receiving port in the receiving repeater set is receiving data;

asserting a port active signal while data is being received by said receiving port; and

maintaining the assertion of said port active signal until a delay time after data is no longer being received by said receiving port.

10. The method of claim 9, wherein said delay time is equal to or greater than said receive channel character delay value.

11. The method of claim 1 wherein the step (d) of providing the character to a transmitting repeater set includes the step of:

providing said character onto an expansion bus.

12. The method of claim 11 wherein said step of providing said character onto an expansion bus includes the steps of:

requesting access to the expansion bus for driving said character onto the expansion bus;

waiting for a contention delay period after said step of requesting access; and

driving said character onto the expansion bus after said step of waiting for a contention delay period and access to said expansion bus is granted.

13. The method of claim 12, wherein said contention delay is equal to or greater than said receive channel character delay value.

14. The method of claim 13, wherein said receive channel character delay value is equal to an arbiter time delay.

15. The method of claim 11 wherein step (d) further includes the step of:

providing a predetermined collision character onto the expansion bus in the logical repeater set when a collision condition exists at a port of the logical repeater set.

16. A repeater set including a repeater unit coupled to a plurality of transceivers, each one of said plurality of transceivers having a receive channel coupled to said repeater unit and a transmit channel coupled to said repeater unit, said repeater set being for use in a logical repeater set in which said repeater set is coupled to other repeater sets by an expansion bus, said repeater set comprising:

a receive channel delay calculator having an output for providing a receive channel character delay value;

a receive channel delay module having a data input coupled to the receive channel of one of the transceivers to receive a receive character to be delayed, a delay input coupled to said output of said receive channel delay calculator and an output for providing a delayed version of said receive character, said receive channel delay module delaying said receive character by said receive channel character delay value in said repeater set in response to receiving said receive character; and

an expansion port having a receive data input coupled to said output of said receive channel delay module, and an expansion bus data interface for coupling to said expansion bus, said expansion port providing said delayed version of said receive character on said expansion bus data interface.

17. The repeater set of claim 16, wherein said expansion port includes:

means for requesting permission to provide said receive character onto said expansion bus data interface; and

means for waiting for at least a contention delay period after making said request before driving said receive character onto said expansion bus data interface.

18. The repeater set of claim 17, wherein the logical repeater set includes an arbiter coupled to said repeater set, wherein said contention delay period is equal to or greater than an arbiter time delay for the arbiter to determine ownership of the expansion bus.

19. The repeater set of claim 17, wherein said contention delay period is equal to or greater than said receive channel character delay value.

20. The repeater set of claim 17, further including:

an arbiter time delay data storage element having an output coupled to said receive channel delay calculator, the data storage element storing a value representing the arbiter time delay.

21. The repeater set of claim 16, wherein said receive channel delay module includes:

a shift register having an input coupled to said data input of said receive channel delay module, said shift register having a plurality of outputs; and

a delay multiplexer having a plurality of data inputs, a select input forming said delay input, and an output forming said output of said delay module, wherein at least one of said plurality of data inputs is coupled to a respective one of said plurality of outputs of said shift register.

22. The repeater set of claim 21, wherein said delay module further includes a data multiplexer having a first input providing a predetermined value, a second input forming said data input of said receive channel delay module, and an output coupled to said input of said shift register, said first input being provided on said output of said data multiplexer when a collision conditions exists in a logical repeater set including said repeater set and at least one port in said repeater set is receiving data.

23. The repeater set of claim 16, wherein said receive channel delay calculator includes a receive channel bit delay calculator for calculating a receive channel bit delay value using the following equation:

##EQU5## wherein;

RBDV is said receive channel character bit delay value,

MAX_-- EOJ_-- R is a value equal to or greater than a largest cessation-of-collision JAM (EOJ) propagation delay value for a receive channel of any transceiver (EOJ(rx)) in the logical repeater set that includes said repeater set,

SOP(rx) is a value substantially equal to a start-of-packet (SOP) propagation delay value of a receive channel of a transceiver in said plurality of transceivers that is providing information to said repeater set,

SOP(A) is an arbiter time delay for the logical repeater set,

EOJ(rc) is a value substantially equal to an EOJ value of the repeater unit and the expansion port of said repeater set, and

SOP(rc) is a value substantially equal to a SOP value of the repeater unit and the expansion port of said repeater set.

24. The repeater set of claim 23, wherein said receive channel delay calculator further includes a receive channel round-up and clamp circuit having an input coupled to said output of said receive channel bit delay calculator to receive said receive channel bit delay value, and an output coupled to said delay input, wherein said receive channel round-up and clamp circuit converts a value provided to said input of said receive channel round-up and clamp circuit into said receive channel character delay value and provides said receive channel character delay value on said output of said receive channel round-up and clamp circuit.

25. The repeater set of claim 24, wherein said receive channel round-up and clamp circuit converts said value provided to said input of said receive channel round-up and clamp circuit into said receive channel character delay value in accordance with the following equation:

##EQU6## wherein;

RCDV is said receive channel character delay value,

RRUCI is said value provided to said input of said receive channel round-up and clamp circuit,

B is a number of bits in said receive character,

INT[RRUCI/B] is equal to a quotient of RRUCI divided by B, if the quotient is an integer, else INT[RRUCI/B] is equal to an integer portion of the quotient plus 1, and

Q is a maximum allowable number of delay periods.

26. The repeater set of claim 24, wherein said receive channel round-up and clamp circuit converts said value provided to said input of said receive channel round-up and clamp circuit into said receive channel character delay value in accordance with the following equation:

space="preserve" listing-type="equation">RCDV=INT[RRUCI/B]

wherein;

RCDV is said receive channel character delay value,

RRUCI is said value provided to said input of said receive channel round-up and clamp circuit,

B is a number of bits in said receive character, and

INT[RRUCI/B] is equal to a quotient of RRUCI divided by B, if the quotient is an integer, else INT[RRUCI/B] is equal to an integer portion of the quotient plus 1.

27. The repeater set of claim 24, wherein said receive channel delay calculator further includes a collision multiplexer having a first input coupled to said output of said receive channel bit delay calculator, a second input coupled to a predetermined collision value, a third input coupled to an output of an arbiter time delay data storage element, and an output coupled to said input of said receive channel round-up and clamp circuit.

28. The repeater set of claim 27, wherein said second input of said collision multiplexer is provided on said output of said collision multiplexer when there is a collision condition in the logical repeater set including said repeater set and said output of said delay module is not idle, and wherein said third input of said collision multiplexer is provided on said output of said collision multiplexer when there is a collision condition in said logical repeater including said repeater set and said output of said delay module is idle.

29. The repeater set of claim 16, further including:

a transmit channel delay calculator having an output for providing a transmit channel character delay value; and

a transmit channel delay module having a data input for receiving a delayed receive character from said expansion bus, a delay input coupled to said output of said transmit channel delay calculator and an output for providing a delayed version of said delayed receive character, said transmit channel delay module delaying said delayed receive character in response to said transmit channel character delay value.

30. The repeater set of claim 29, wherein said output of said transmit channel delay module is coupled to transmit channels of at least two transceivers in said plurality of transceivers.

31. The repeater set of claim 29, wherein said transmit channel delay module includes:

a shift register having an input coupled to said data input of said transmit channel delay module, said shift register having a plurality of outputs; and

a delay multiplexer having a plurality of data inputs, a select input forming said delay input, and an output forming said output of said transmit channel delay module, wherein at least one of said plurality of data inputs is coupled to a respective one of said plurality of outputs of said shift register in said transmit channel delay module.

32. The repeater set of claim 29, wherein said transmit channel delay calculator includes a transmit channel bit delay calculator for calculating a transmit channel bit delay value using the following equation:

##EQU7## wherein;

TBDV is said transmit channel bit delay value for a transmit channel of a transceiver in said plurality of transceivers,

MAX_-- EOJ_-- T is a value equal to or greater than a largest EOJ value for a transmit channel of any transceiver (EOJ(tx)) in the logical repeater set including said repeater set,

SOP(tx) is a value substantially equal to a SOP value of said transmit channel of said transceiver in said plurality of transceivers for which TBDV is being calculated,

EOJ(tc) is a value substantially equal to an EOJ value of the repeater unit and the expansion port in said repeater set, and

SOP(rc) is a value substantially equal to a SOP value of the repeater unit and the expansion port in said repeater set.

33. The repeater set of claim 32, wherein said transmit channel delay calculator further includes a transmit channel round-up and clamp circuit having an input coupled to said output of said transmit channel bit delay calculator to receive said transmit channel bit delay value, and an output coupled to said delay input of said transmit channel delay module, wherein said transmit channel round-up and clamp circuit converts a value provided to said input of said transmit channel round-up and clamp circuit into a transmit channel character delay value and provides said transmit channel character delay value on said output of said transmit channel round-up and clamp circuit.

34. The repeater set of claim 33, wherein said transmit channel round-up and clamp circuit converts said value provided to said input of said transmit channel round-up and clamp circuit into said transmit channel character delay value in accordance with the following equation:

##EQU8## wherein;

TCDV is said transmit channel character delay value,

TRUCI is said value provided to said input of said transmit channel round-up and clamp circuit,

B is a number of bits in said delayed receive character,

INT[TRUCI/B] is equal to a quotient of TRUCI divided by B, if the quotient is an integer, else INT[TRUCI/B] is equal to an integer portion of the quotient plus 1, and

Q is a maximum allowable number of delay periods.

35. The repeater set of claim 33, wherein said transmit channel round-up and clamp circuit converts said transmit channel bit delay value into said transmit channel character delay value in accordance with the following equation:

space="preserve" listing-type="equation">TCDV=INT[TRUCI/B]

wherein;

TCDV is said transmit channel character delay value,

TRUCI is said value provided to said input of said transmit channel round-up and clamp circuit,

B is a number of bits in said delayed receive character, and

INT[TRUCI/B] is equal to a quotient of TRUCI divided by B, if the quotient is an integer, else INT[TRUCI/B] is equal to an integer portion of the quotient plus 1.

36. The repeater set of claim 33, wherein said transmit channel delay calculator further includes a collision multiplexer having a first input coupled to said output of said transmit channel bit delay calculator, a second input coupled to a predetermined collision value, and an output coupled to said input of said transmit channel round-up and clamp circuit.

37. The repeater set of claim 36, wherein said second input of said collision multiplexer is provided on said output of said collision multiplexer when there is a collision condition in the logical repeater set including said repeater set.

38. The repeater set of claim 16, further including:

a set of data storage elements having outputs coupled to said receive channel delay calculator.

39. The repeater set of claim 38, further including:

a user interface bus coupled to inputs of a portion of data storage elements in said set of data storage, for providing data to said data storage elements.

40. The repeater set of claim 29, further including:

a set of data storage elements having outputs coupled to said transmit channel delay calculator.

41. The repeater set of claim 40, further including:

a user interface bus coupled to inputs of a portion of data storage elements in said set of data storage, for providing data to said data storage elements.