Flash memory system having memory cache

• US 6,026,027 A
• Filed: 04/25/1995
• Issued: 02/15/2000
• Est. Priority Date: 01/31/1994
• Status: Expired due to Term

• Current Assignee: Visual Memory LLC (Endpoint IP LLC)
• Original Assignee: Norand Corporation (Baker Hughes Company)
• Inventors: Terrell, II, James Richard, Beard, Paul
• Primary Examiner(s): Fears, Terrell W.
• Application Number:
  US08/428,856
• Time in Patent Office: 1,757 Days
• Field of Search: 365/185.33, 365/63, 365/73, 365/103, 365/104, 365/185.09, 365/189.12
• US Class Current: 365/185.33
• CPC Class Codes: G06F 12/0246 in block erasable memory, e.g. flash memory
• CPC Class Codes: G06F 12/0875 with dedicated cache, e.g. instruction or stack
• CPC Class Codes: G06F 2212/7203 Temporary buffering, e.g. using volatile buffer or dedicated buffer blocks
• CPC Class Codes: G06F 2212/7211 Wear leveling

Abstract

The present invention discloses an electronic memory system having semipermanent memory storage, a memory device for rapid data transfer and temporary memory storage, and controller for monitoring and controlling writes to the semipermanent memory storage.

Claims

1. An electronic memory system comprising:

(a) a first memory device for semipermanent memory storage;

(b) a second memory device for rapid data transfer and temporary memory storage; and

(c) a controller operatively connected with said first and second memory devices for monitoring and controlling writes to said first memory device such that successive write operations to said first memory device are made successively to all sections of first memory device.

2. The electronic memory storage system of claim 1 wherein said first memory device comprises flash memory.

3. The electronic memory storage system of claim 1 wherein said second memory device comprises control logic for writing and reading said data to and from said first memory device.

4. The electronic memory storage system of claim 1 wherein said controller comprises control logic for controlling the allocation and distribution of writes to said first memory device so that data to be written to said first memory device is saved to said second memory device until an entire block has been saved and then writing said saved entire block to said first memory device.

5. The memory storage system of claim 1 wherein said controller utilizes standard hard disk drive formatting.

6. The memory storage system of claim 1 wherein said controller utilizes standard file allocation table hard disk drive formatting.

7. The memory storage system of claim 1 wherein said second memory device comprises static random access memory.

8. The memory storage system of claim 1 wherein said second memory device comprises expanded memory.

9. The memory storage system of claim 1 wherein said controller utilizes a standard basic input output system.

10. The memory storage system of claim 1 wherein said controller utilizes a terminate-and-stay-resident memory resident program.

11. The memory storage system of claim 1 wherein said controller comprises a cyclic address counter.

22. The memory storage system of claim 1 wherein said controller utilizes a terminate-and-stay-resident memory resident program.

23. The memory storage system of claim 1 wherein said controller comprises a cyclic address counter.

12. A method for implementing a flash memory device using standard hard disk drive memory formatting and for controlling the wear thereof, comprising:

(a) writing the data to be saved in the flash memory device first to a memory cache until an entire block of memory has been saved therein; and

(b) thereafter writing the entire saved memory block from the memory cache to the flash memory device.

13. The method of claim 12 further comprising the step of allocating write locations of said flash memory device so that successive write operations are distributed to all sections of flash memory device.

14. An electronic memory system comprising:

(a) a first memory device for semipermanent memory storage;

(b) a second memory device for rapid data transfer and temporary memory storage; and

(c) a controller operatively connected with said first and second memory devices for monitoring and controlling writes to said first memory device so that data to be written to said first memory device is saved to said second memory device until an entire block has been saved and then writing said saved entire block to said first memory device.

15. The electronic memory storage system of claim 14 wherein said first memory device is flash memory.

16. The electronic memory storage system of claim 14 wherein said second memory device comprises control logic for writing and reading said data to and from said first memory device.

17. The memory storage system of claim 14 wherein said controller utilizes standard hard disk drive formatting.

18. The memory storage system of claim 14 wherein said controller utilizes standard file allocation table hard disk drive formatting.

19. The memory storage system of claim 14 wherein said second memory device comprises static random access memory.

20. The memory storage system of claim 14 wherein said second memory device comprises expanded memory.

21. The memory storage system of claim 14 wherein said controller utilizes a standard basic input output system.

24. A method for implementing a flash memory device and for controlling the wear thereof, comprising:

(a) writing the data to be saved in the flash memory device first to a memory cache until an entire block of memory has been saved therein;

(b) allocating write locations of said flash memory device so that successive write operations are distributed to all sections of flash memory device; and

(c) thereafter writing the data from the memory cache to the flash memory device.