Integrated circuit memory devices having improved precharge and I/O driver characteristics and methods of operating same
First Claim
1. An integrated circuit memory device, comprising:
- a pair of complementary input/output lines;
a pair of complementary data lines;
means, responsive to a driver signal, for driving said pair of complementary input/output lines with complementary data from said pair of complementary data lines when the driver signal is in an enabled state; and
means, responsive to both a precharge control signal and the driver signal, for precharging said pair of complementary input/output lines during a precharge time interval, said precharge time interval commencing when the driver signal and the precharge control signal are in disabled and enabled states, respectively, at the same time, and terminating upon transition of the driver signal from its disabled state to an enabled state even if the precharge control signal remains in its enabled state.
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Accused Products
Abstract
Integrated circuit memory devices include a pair of complementary input/output lines (IO and /IO), a pair of complementary data lines (DATA and /DATA) and a driver circuit which is responsive to a driver signal (PDT) and drives the pair of complementary input/output lines with complementary data from the pair of complementary data lines when the driver signal is in an enabled state (e.g., logic 1). A precharge circuit is also provided. This precharge circuit, which is responsive to a precharge control signal (PIOPR) and the driver signal (PDT), precharges the pair of complementary input/output lines IO and /IO during a precharge time interval which precedes the generation of a column select signal (CSL). The precharge time interval commences when the driver signal (PDT) and the precharge control signal (PIOPR) are in disabled and enabled states, respectively, at the same time. The precharge time interval also terminates upon transition of the driver signal (PDT) from its disabled state to an enabled state, even if the precharge control signal remains in its enabled state.
28 Citations
19 Claims
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1. An integrated circuit memory device, comprising:
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a pair of complementary input/output lines; a pair of complementary data lines; means, responsive to a driver signal, for driving said pair of complementary input/output lines with complementary data from said pair of complementary data lines when the driver signal is in an enabled state; and means, responsive to both a precharge control signal and the driver signal, for precharging said pair of complementary input/output lines during a precharge time interval, said precharge time interval commencing when the driver signal and the precharge control signal are in disabled and enabled states, respectively, at the same time, and terminating upon transition of the driver signal from its disabled state to an enabled state even if the precharge control signal remains in its enabled state. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9)
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10. An integrated circuit memory device, comprising:
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a pair of complementary input/output lines; a pair of complementary data lines; a driver circuit, responsive to a driver signal, to drive said pair of complementary input/output lines with complementary data from said pair of complementary data lines when the driver signal is in an enabled state; and a precharge circuit, responsive to a precharge control signal and the driver signal, to precharge said pair of complementary input/output lines during a precharge time interval, said precharge time interval commencing when the driver signal and the precharge control signal are in disabled and enabled states, respectively, at the same time, and terminating upon transition of the driver signal from its disabled state to an enabled state even if the precharge control signal remains in its enabled state. - View Dependent Claims (11, 12, 13, 14, 15, 16, 17, 18)
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19. A method of operating an integrated circuit memory device, comprising the steps of:
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generating an enabled column select signal and an enabled precharge control signal during respective nonoverlapping time intervals; driving a pair of complementary input/output lines with write data, in response to a driver signal which is enabled during a portion of a write time interval when the precharge control signal is also enabled; and precharging the complementary input/output lines during another portion of the write time interval when the precharge control signal is enabled and the driver signal is disabled.
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Specification