Transition-controlled digital encoding and signal transmission system

• US 6,026,124 A
• Filed: 06/12/1998
• Issued: 02/15/2000
• Est. Priority Date: 10/05/1995
• Status: Expired due to Term

• Current Assignee: Silicon Image, Inc. (Lattice Semiconductor Corporation)
• Original Assignee: Silicon Image, Inc. (Lattice Semiconductor Corporation)
• Inventors: Lee, Kyeongho, Jeong, Deog-Kyon
• Primary Examiner(s): Pham, Chi H.
• Assistant Examiner(s): Tran, Khai
• Application Number:
  US09/097,021
• Time in Patent Office: 613 Days
• Field of Search: 375/292, 375/290, 375/253, 370/473, 341/58, 341/59, 369/50, 369/59, 369/58, 369/24, 369/48, 714/758
• US Class Current: 375/292
• CPC Class Codes: H04L 2007/045 Fill bit or bits, idle words
• CPC Class Codes: H04L 25/03866 using scrambling
• CPC Class Codes: H04L 25/085 Arrangements for reducing interference in line transmission systems, e.g. by differential transmission
• CPC Class Codes: H04L 25/4915 using pattern inversion or substitution H04L25/4908 takes precedence
• CPC Class Codes: H04L 7/0008 Synchronisation information channels, e.g. clock distribution lines
• CPC Class Codes: H04N 21/2368 Multiplexing of audio and video streams
• CPC Class Codes: H04N 21/4341 Demultiplexing of audio and video streams
• CPC Class Codes: H04N 7/083 with signal insertion during the vertical and the horizontal blanking interval , e.g. MAC data signals
• CPC Class Codes: H04N 7/52 Systems for transmission of a pulse code modulated video signal with one or more other pulse code modulated signals, e.g. an audio signal or a synchronizing signal assembling of a multiplex stream by combining a video stream with other content or additional data, remultiplexing of multiplex streams, insertion of stuffing bits into the multiplex stream, assembling of a packetised elementary stream at server side H04N21/236; disassembling of a multiplex stream, remultiplexing of multiplex streams, extraction or processing of Service Information, disassembling of packetised elementary stream at client side H04N21/434

Abstract

A method and apparatus for producing a transition-controlled, DC-balanced sequence of characters from an input sequence of data bytes is disclosed herein. The bits in each of the data bytes are selectively complemented in accordance with the number of logical `1` signals in each data byte in order to produce selectively complemented data blocks. A cumulative disparity is then determined between the logical values of different type included within ones of the selectively complemented data blocks previously encoded into characters. In addition, a current disparity in a candidate character associated with a current one of the selectively complemented data blocks being encoded is also determined. The candidate character is assigned to the current one of the selectively complemented data blocks if the current disparity is of a polarity opposite to a first polarity of the cumulative disparity. Alternately, the complement of the candidate character is assigned to the current one of the selectively complemented data blocks if the current disparity is of the first polarity. In a high-transition mode of operation, the bits within data blocks including fewer than a minimum number of logical `1` signals are selectively complemented so that each such selectively complemented data block includes in excess of the minimum number of logical transitions. In a low-transition mode of operation, the bits within data blocks having more than a predefined number of logical `1` signals are selectively complemented so that each such selectively complemented data block includes less than the maximum number of logical transitions.

In one embodiment, an input sequence of 9-bit data blocks is balanced to produce a DC-balanced sequence of characters. A shift register generator generates a pseudo-random binary sequence. Two bits of the pseudo-random binary sequence are logically combined to determine whether to invert another bit in the pseudo-random binary sequence, thereby cycling the pseudo-random binary sequence. A bit of the pseudo-random binary sequence is used as a criterion to selectively invert all the bits in the incoming 9-bit data block, thereby producing a 9-bit data block in an output stream that, over time, tends to be DC-balanced.

Claims

1. A method of producing a transition-optimized DC-balanced sequence of characters from an input sequence of data blocks, said method including the steps of:

receiving one input data block from said input sequence of data blocks, said input data block consisting of N bits, where N is a positive integer;

generating a transition-optimized DC-balanced data block from said transition-optimized data block by

determining the number of transitions between adjacent bits in the input data block and selectively performing an inversion operation on said input data block as a function of said determination in order to produce a transition optimized data block,

determining a DC-balance of said transition optimized data block, comparing said DC-balance with a previously accumulated DC balance and selectively performing an inversion operation on said transition optimized data block as a function of said comparison, thereby creating said transition-optimized DC-balanced data block consisting of fewer than N+2 data bits.

2. The method of claim 1, wherein N is equal to 8.

3. A method of producing a DC-balanced sequence of characters from an input sequence of data blocks, said method including the steps of:

receiving a first input data block in the input sequence of data blocks, said first input data block consisting of N bits, where N is a positive integer;

generating a first DC-balanced data block from said first input data block, said first DC-balanced data block consisting of at most N bits;

receiving a next input data block in the input sequence of data blocks, said next input data block consisting of N bits, wherein N is a positive integer;

generating a next DC-balanced data block from said next input data block, said next DC-balanced data block consisting of at most N bits; and

combining the first DC balanced data block with the next DC balanced data block in order to produce said DC balanced sequence of characters.

4. The method of claim 3, wherein N is equal to 8.

5. The method of claim 3, wherein N is equal to 9.

6. An apparatus for producing a transition-optimized DC-balanced data block from an input data block, said apparatus comprising:

means for receiving one input data block from said input sequence of data blocks, said input data block consisting of N bits, wherein N is a positive integer;

a transition counter for determining the number of logical transitions between adjacent bits in the input data block;

a conditional alternate bit inversion logic for generating a transition-optimized data block from said input data block, wherein said conditional alternate bit inversion logic inverts a select group of bits within the input data block as function of the number of logical transitions determined by the transition counter;

a DC balancing module for generating the transition-optimized DC-balanced data block from said transition-optimized data block by comparing a current disparity with a cumulative disparity, said transition-optimized DC-balanced data block consisting of fewer than N+2 data bits.

7. The apparatus of claim 6, wherein N is equal to 8.

8. An apparatus for producing a DC-balanced encoded frame from an input frame having N bits, where N is a positive integer, said apparatus comprising:

a shift register generator having an output value and N serially coupled single bit shift registers, wherein the shift register generator is loaded with a pseudo-random binary sequence, with each single bit shift having a predetermined value in the sequence, and further wherein the contents of each single bit shift register is loaded into a next higher order shift register as the shift register generator is clocked with the contents of a last single bit shift register in the N serially coupled shift registers being the output value;

an exclusive-or circuit for combining the predetermined values in a select two of the single bit shift registers and loading an output from the exclusive-or circuit into the first single bit shift register;

means for receiving and inverting the input frame;

a selector circuit for selectively outputting one of two inputs with a first input for receiving the inverted input frame from the means for inverting and a second input for receiving the input frame, wherein the selector circuit is coupled to the shift register generator and selectively outputs one of the two inputs as a function of the output value.

9. The apparatus of claim 8, wherein N is equal to 8.

10. The apparatus of claim 9, wherein N is equal to 9.