Method and apparatus for eliminating the transpose buffer during a decomposed forward or inverse 2-dimensional discrete cosine transform through operand decomposition storage and retrieval

• US 6,026,217 A
• Filed: 06/21/1996
• Issued: 02/15/2000
• Est. Priority Date: 06/21/1996
• Status: Expired due to Term

• Current Assignee: Hewlett-Packard Development Company, L.P. (HP Inc.)
• Original Assignee: Digital Equipment Corporation (HP Inc.)
• Inventors: Adiletta, Matthew J.
• Primary Examiner(s): Trammell, James P.
• Assistant Examiner(s): ASSOUAD, PATRICK J
• Application Number:
  US08/668,480
• Time in Patent Office: 1,334 Days
• Field of Search: 395/200.77, 395/445, 395/454, 395/458, 395/472, 395/280, 395/821, 395/849, 395/872, 395/878, 395/561, 364/725
• US Class Current: 709/247
• CPC Class Codes: H04N 19/126 Details of normalisation or weighting functions, e.g. normalisation matrices or variable uniform quantisers
• CPC Class Codes: H04N 19/14 Coding unit complexity, e.g. amount of activity or edge presence estimation H04N19/146 takes precedence
• CPC Class Codes: H04N 19/149 by estimating the code amount by means of a model, e.g. mathematical model or statistical model
• CPC Class Codes: H04N 19/15 by monitoring actual compressed data size at the memory before deciding storage at the transmission buffer
• CPC Class Codes: H04N 19/152 by measuring the fullness of the transmission buffer
• CPC Class Codes: H04N 19/159 Prediction type, e.g. intra-frame, inter-frame or bidirectional frame prediction
• CPC Class Codes: H04N 19/169 characterised by the coding unit, i.e. the structural portion or semantic portion of the video signal being the object or the subject of the adaptive coding
• CPC Class Codes: H04N 19/176 the region being a block, e.g. a macroblock
• CPC Class Codes: H04N 19/177 the unit being a group of pictures [GOP]
• CPC Class Codes: H04N 19/192 the adaptation method, adaptation tool or adaptation type being iterative or recursive
• CPC Class Codes: H04N 19/42 characterised by implementation details or hardware specially adapted for video compression or decompression, e.g. dedicated software implementation H04N19/635 takes precedence
• CPC Class Codes: H04N 19/423 characterised by memory arrangements H04N19/433 takes precedence
• CPC Class Codes: H04N 19/61 in combination with predictive coding

Abstract

A method and apparatus is presented for video image compression using a unique operand decomposition technique combined with an innovative data scatter and retrieve process. This combination of features allows the use of single ported RAM structures where multiported RAMS would normally be used, such as when retrieving two operands in the same time cycle. As applied to the Discrete Cosine Transformation this method and apparatus additionally allows elimination of the usual prior art use of a separate transpose matrix buffer. The elimination of the separate transpose matrix buffer is accomplished by combining the transpose matrix intermediate results memory storage with the memory buffer used for the other intermediate results in a double buffer system. The double buffer memory locations are chosen so that the intermediate storage register address are orthogonal to the initial source addresses, thereby using one of the properties of the Discrete Cosine Transform to improve speed of operation and reduce the circuit area and system cost.

Claims

1. An apparatus for controlling a plurality of data elements, comprising:

a single bank memory for storing said data elements, said memory consisting of single ported RAM cells,

an assignment table which specifies storage locations within said memory for all of said data elements based upon a predetermined relationship between said data elements, and

an access circuit coupled to said memory for simultaneously retrieving at least two of said stored data elements from said memory.

2. An apparatus for performing a discrete cosine transformation and an inverse discrete cosine transformation, comprising:

means for receiving a plurality of data elements for transformation,

means for determining a specific order for storage of said data elements,

means for storing said data elements in a single bank memory buffer according to said specific order, said memory buffer comprising a single ported RAM structure; and

means for substantially simultaneously retrieving a pair of said data elements from said memory buffer in each memory cycle.

3. The apparatus of claim 2 wherein said apparatus for performing a discrete cosine transformation and an inverse discrete cosine transformation further comprises;

a discrete cosine transformation circuit,

a quantization transformation circuit, and

wherein said single bank memory buffer comprises a single double buffer memory element logically connected between said discrete cosine transformation circuit and said quantization transformation circuit, wherein said single double buffer memory element is the only buffer memory element.

4. A method for video signal compression and decompression, comprising:

receiving a video signal comprised of data elements;

performing at least one of a discrete cosine transform and a quantization transform on said video signal utilizing a single double buffer memory element, wherein said performing step further includes the steps of,

storing said data elements in said double buffer memory element, said double buffer memory element being comprised of single ported RAM cells, said storing step further comprising the steps of,

storing an initial operand in each of said single ported RAM cells via the use of a specific ordering of said initial operands in said buffer,

retrieving a selected pair of said initial operands from said double buffer memory in a single memory cycle,

transmitting said pair of said initial operands to a circuit for performing at least one of said discrete cosine transform and quantization transform on said video signal,

receiving an intermediate transformed value of each of said initial operands from said circuit,

storing in the same ones of said single ported RAM cells said intermediate transformed values of said initial operands, and

performing said discrete cosine transform and said quantization transform to generate at least one of a compressed video signal and a decompressed video signal.

5. A method for video signal decompression, comprising:

receiving a compressed video signal comprised of data elements;

performing at least one of an inverse discrete cosine transform and an inverse quantization transform on said video signal utilizing a single double buffer memory element, wherein said performing step further includes the steps of,

storing said data elements in said double buffer memory element, said double buffer memory element being comprised of single ported RAM cells, said storing step further comprising the steps of,

storing an initial operand in each of said single ported RAM cells via the use of a specific ordering of said initial operands in said buffer,

retrieving a pair of said initial operands from said double buffer memory in a single memory cycle,

transmitting said pair of said initial operands to one of said transform means,

receiving an intermediate transformed value of each of said initial operands from said transform means,

storing in the same ones of said single ported RAM cells said intermediate transformed values of said initial operands, and

performing said inverse discrete cosine transform and said inverse quantization transform to generate a decompressed video signal.