Programmable clock manager for a programmable logic device that can generate at least two different output clocks

  • US 6,028,463 A
  • Filed: 10/15/1997
  • Issued: 02/22/2000
  • Est. Priority Date: 10/15/1997
  • Status: Expired due to Term
First Claim
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1. A programmable logic device (PLD) having at least one programmable clock manager (PCM), the PCM comprising:

  • (a) at least one input port configured to receive an input clock;

    (b) a PCM core function block programmably configurable to convert the input clock into at least two different output clocks having different programmable clock rates; and

    (c) at least two output ports configured to transmit the at least two different output clocks.

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