Programmable clock manager for a programmable logic device that can generate at least two different output clocks

• US 6,028,463 A
• Filed: 10/15/1997
• Issued: 02/22/2000
• Est. Priority Date: 10/15/1997
• Status: Expired due to Term

• Current Assignee: Lattice Semiconductor Corporation
• Original Assignee: Lucent Technologies, Inc. (Nokia Corporation)
• Inventors: Albu, Lucian R., Zilic, Zeljko, Leung, Wai-Bor, Britton, Barry K., Thompson, James A., Stuby, Richard G. Jr.
• Primary Examiner(s): Wells, Kenneth B.
• Application Number:
  US08/949,992
• Time in Patent Office: 860 Days
• Field of Search: 327/298, 327/164, 327/212, 327/291, 326/38, 326/39, 326/40, 326/93, 326/37
• US Class Current: 327/291
• CPC Class Codes: G06F 1/06 Clock generators producing several clock signals G06F1/08 - G06F1/14 take precedence
• CPC Class Codes: G06F 1/08 Clock generators with changeable or programmable clock frequency
• CPC Class Codes: H03K 19/1733 Controllable logic circuits H03K19/177 takes precedence
• CPC Class Codes: H03K 19/17704 the logic functions being realised by the interconnection of rows and columns
• CPC Class Codes: H03K 19/1774 for global signals, e.g. clock, reset
• CPC Class Codes: H03L 7/0816 the controlled phase shifter and the frequency- or phase-detection arrangement being connected to a common input
• CPC Class Codes: H03L 7/0891 the up-down pulses controlling source and sink current generators, e.g. a charge pump

Abstract

A programmable logic device (PLD), such as a field programmable gate array (FPGA), has a programmable clock manager (PCM) that converts an input clock into at least two different output clocks having different clock rates. The different output clocks can be used to control different processes either within or outside the FPGA. For example, one output clock can be used to control the FPGA'"'"'s input/output registers, while a second, faster output clock can be used to control the FPGA'"'"'s internal registers.

Claims

1. A programmable logic device (PLD) having at least one programmable clock manager (PCM), the PCM comprising:

(a) at least one input port configured to receive an input clock;

(b) a PCM core function block programmably configurable to convert the input clock into at least two different output clocks having different programmable clock rates; and

(c) at least two output ports configured to transmit the at least two different output clocks.

2. The invention of claim 1, wherein the PLD is a field programmable gate array (FPGA).

3. The invention of claim 1, wherein a first output clock is used to drive processing internal to the PLD and a second output clock is used to drive input/output (I/O) operations for the PLD.

4. The invention of claim 3, wherein the first clock rate is higher than the second clock rate.

5. The invention of claim 1, wherein:

the clock rate R_O1 of a first output clock is given by;

space="preserve" listing-type="equation">R.sub.O1= R.sub.I ·

D0/D1

where R_I is the clock rate of the input clock, and

the clock rate R_O2 of a second output clock is given by;

space="preserve" listing-type="equation">R.sub.O2 =R.sub.O1 ·

D2

where D0, D1, and D2 are independently programmable parameters.

6. The invention of claim 1, wherein the PCM is adapted to be programmed during PLD operations, without reconfiguring the PLD.

7. The invention of claim 1, wherein the PCM is adapted to be disabled to save power, when the input clock is not converted by the PCM.

8. The invention of claim 1, wherein the PCM can be configured to operate as a system component that is functionally independent of operations of the rest of the PLD, such that the PCM is adapted to be reset and/or reprogrammed without affecting the rest of the PLD, and the rest of the PLD can be reset and/or reprogrammed without affecting the PCM.

9. A programmable logic device (PLD) having at least one programmable clock manager (PCM), the PCM comprising:

(a) at least one input port configured to receive an input clock;

(b) a PCM core function block configured to convert the input clock into at least two different output clocks having different clock rates; and

(c) at least two output ports configured to transmit the at least two different output clocks, wherein a first output clock is used to drive processing internal to the PLD and a second output clock is used to drive I/O operations for the PLD.

10. The invention of claim 9, wherein the first clock rate is higher than the second clock rate.

11. The invention of claim 9, wherein:

the clock rate R_O1 of the first output clock is given by;

space="preserve" listing-type="equation">R.sub.O1 =R.sub.I D0/D1

where R_I is the clock rate of the input clock; and

the clock rate R_O2 of the second output clock is given by;

space="preserve" listing-type="equation">R.sub.O2 =R.sub.O1 ·

D2

where D0, D1, and D2 are independently programmable parameters.

12. The invention of claim 9, wherein the PCM is adapted to be programmed during PLD operations, without reconfiguring the PLD.

13. The invention of claim 9, wherein the PCM is adapted to be disabled to save power, when the input clock is not converted by the PCM.

14. The invention of claim 9, wherein the PCM can be configured to operate as a system component that is functionally independent of operations of the rest of the PLD, such that the PCM is adapted to be reset and/or reprogrammed without affecting the rest of the PLD, and the rest of the PLD can be reset and/or reprogrammed without affecting the PCM.

15. The invention of claim 9, wherein:

the first clock rate is higher than the second clock rate;

the clock rate R_O1 of the first output clock is given by;

space="preserve" listing-type="equation">R.sub.O1 =R.sub.I ·

D0/D1

where R_I is the clock rate of the input clock;

the clock rate R_O2 of the second output clock is given by;

space="preserve" listing-type="equation">R.sub.O2 =R.sub.O1 ·

D2

where D0, D1, and D2 are independently programmable parameters;

the PCM is adapted to be programmed during PLD operations, without reconfiguring the PLD;

the PCM is adapted to be disabled to save power, when the input clock is not converted by the PCM; and

the PCM can be configured to operate as a system component that is functionally independent of operations of the rest of the PLD, such that the PCM is adapted to be reset and/or reprogrammed without affecting the rest of the PLD, and the rest of the PLD can be reset and/or reprogrammed without affecting the PCM.

16. A programmable logic device (PLD) having at least one programmable clock manager (PCM), the PCM comprising:

(a) at least one input port configured to receive an input clock;

(b) a PCM core function block configured to convert the input clock into at least two different output clocks having different clock rates; and

(c) at least two output ports configured to transmit the at least two different output clocks, wherein;

the clock rate R_O1 of a first output clock is given by;

space="preserve" listing-type="equation">R.sub.O1 =R.sub.I ·

D0/D1

where R_I is the clock rate of the input clock; and

the clock rate R_O2 of a second output clock is given by;

space="preserve" listing-type="equation">R.sub.O2 =R.sub.O1 ·

D2

where D0, D1, and D2 are independently programmable parameters.

17. The invention of claim 16, wherein the PCM is adapted to be programmed during PLD operations, without reconfiguring the PLD.

18. The invention of claim 16, wherein the PCM is adapted to be disabled to save power, when the input clock is not converted by the PCM.

19. The invention of claim 16, wherein the PCM can be configured to operate as a system component that is functionally independent of operations of the rest of the PLD, such that the PCM is adapted to be reset and/or reprogrammed without affecting the rest of the PLD, and the rest of the PLD can be reset and/or reprogrammed without affecting the PCM.

20. A programmable logic device (PLD) having at least one programmable clock manager (PCM), the PCM comprising:

(a) at least one input port configured to receive an input clock;

(b) a PCM core function block configured to convert the input clock into at least two different output clocks having different clock rates; and

(c) at least two output ports configured to transmit the at least two different output clocks, wherein the PCM is adapted to be programmed during PLD operations, without reconfiguring the PLD.

21. The invention of claim 20, wherein the PCM is adapted to be disabled to save power, when the input clock is not converted by the PCM.

22. The invention of claim 20, wherein the PCM can be configured to operate as a system component that is functionally independent of operations of the rest of the PLD, such that the PCM is adapted to be reset and/or reprogrammed without affecting the rest of the PLD, and the rest of the PLD can be reset and/or reprogrammed without affecting the PCM.

23. A programmable logic device (PLD) having at least one programmable clock manager (PCM), the PCM comprising:

(a) at least one input port configured to receive an input clock;

(b) a PCM core function block configured to convert the input clock into at least two different output clocks having different clock rates; and

(c) at least two output ports configured to transmit the at least two different output clocks, wherein the PCM is adapted to be programmed during PLD operations, without reconfiguring the PLD, wherein the PCM can be configured to operate as a system component that is functionally independent of operations of the rest of the PLD, such that the PCM is adapted to be reset and/or reprogrammed without affecting the rest of the PLD, and the rest of the PLD can be reset and/or reprogrammed without affecting the PCM.

24. The invention of claim 23, wherein the PCM is adapted to be disabled to save power, when the input clock is not converted by the PCM.