Solid-state imaging device

• US 6,031,571 A
• Filed: 05/23/1997
• Issued: 02/29/2000
• Est. Priority Date: 05/30/1996
• Status: Expired due to Fees

• Current Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Original Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Inventors: Arakawa, Kenichi
• Primary Examiner(s): Ho, Tuan
• Assistant Examiner(s): FERGUSON, ERIC M
• Application Number:
  US08/863,019
• Time in Patent Office: 1,012 Days
• Field of Search: 348/314, 348/321, 348/323, 257/288, 257/379, 257/536, 377/60, 327/142, 327/143
• US Class Current: 348/316
• CPC Class Codes: G11C 19/285 Peripheral circuits, e.g. for writing into the first stage; for reading-out of the last stage
• CPC Class Codes: H04N 25/00 Circuitry of solid-state image sensors [SSIS]; Control thereof
• CPC Class Codes: H04N 25/73 using interline transfer [IT]
• CPC Class Codes: H04N 25/75 Circuitry for providing, modifying or processing image signals from the pixel array

Abstract

A solid-state imaging device has a storage section formed on a surface portion of a semiconductor substrate to receive and store signal charges, a discharge section formed on the surface portion of the substrate at a predetermined distance from the storage section, a reset section constituted by a depletion-type MOS transistor formed between the storage section and the discharge section, and reset voltage setting means for setting a voltage of a reset pulse to be applied to the reset section. The reset voltage setting section has first and second resistive elements series-connected between one end to which a predetermined voltage is applied and the other end which is grounded. A node which connects the first resistive element to the second resistive element is connected to a reset voltage application electrode. The second resistive element consists of a depletion-type MOS transistor, and the depletion-type MOS transistor has a depletion-type impurity layer formed by the same process as that of a depletion-type impurity layer of the reset section.

Claims

1. A solid-state imaging device comprising:

a storage section which is formed on a surface portion of a semiconductor substrate to receive and store signal charges;

a discharge section formed on the surface portion of the semiconductor substrate at a predetermined distance from said storage section;

a reset section constituted by a depletion-type MOS transistor formed between said storage section and said discharge section; and

a reset voltage setting section for setting a voltage of a reset pulse to be applied to said reset section,

wherein said reset voltage setting section has a resistive element and a depletion-type MOS transistor series-connected between one end to which a predetermined voltage is applied and the other end which is grounded, and a node for connecting said resistive element to said depletion-type MOS transistor, the node is connected to a reset voltage application electrode, and said depletion-type MOS transistor has a depletion-type impurity layer formed by the same process as that for a depletion-type impurity layer of said reset section.

2. A device according to claim 1, wherein said reset voltage setting section sets a voltage of the reset pulse within a saturation region of said depletion-type MOS transistor included in said reset voltage setting section.

3. A device according to claim 1, wherein said resistive element comprises a diffused resistor.

4. A device according to claim 1, wherein said resistive element comprises an enhancement-type MOS transistor.

5. A device according to claim 1, wherein said depletion-type impurity layer included in said reset voltage setting section has a substantially same impurity concentration as that of said depletion-type impurity layer of said reset section.

6. A solid-state imaging device comprising:

a floating diffusion layer which is formed on a surface portion of a semiconductor substrate to receive and store signal charges transferred from an adjacent CCD;

a reset drain formed on the surface portion of the semiconductor substrate to oppose said floating diffusion layer through a channel region;

a reset gate electrode which is formed on said channel region through an insulating film, and electrically connects said floating diffusion layer to said reset drain through said channel region upon application of a reset pulse to transfer the signal charges stored in said floating diffusion layer to said reset drain; and

a reset voltage setting circuit for setting a voltage of the reset pulse to be applied to said reset gate electrode,

wherein said reset voltage setting circuit has a resistive element and a depletion-type MOS transistor series-connected between one end to which a predetermined voltage is applied and the other end which is grounded, and a node for connecting said resistive element to said depletion-type MOS transistor, the node is connected to said reset gate electrode, a channel region of said depletion-type MOS transistor being provided by the same process as that for said channel region of a depletion-type reset transistor including said floating diffusion layer, said reset drain, and said reset gate electrode.

7. A device according to claim 6, wherein said reset voltage setting circuit sets a voltage of the reset pulse within a saturation region of said depletion-type MOS transistor included in said reset voltage setting circuit.

8. A device according to claim 6, wherein said reset voltage setting circuit includes said depletion-type MOS transistor manufactured by the same process as that for a depletion-type reset transistor constituted by said floating diffusion layer, said channel region, said reset drain, and said reset gate electrode, so that an amount of change in impurity concentration of said channel region of said reset transistor due to variations in manufacturing process is substantially the same as an amount of change in impurity concentration of said channel region of said depletion-type transistor included in said reset voltage setting circuit, and when the impurity concentration of said channel region of said reset transistor changes owing to variations in manufacturing process, the voltage of the reset pulse set by said reset voltage setting circuit changes to cancel out the change in impurity concentration.

9. A device according to claim 6, wherein said resistive element comprises a diffused resistor.

10. A device according to claim 6, wherein said resistive element comprises an enhancement-type MOS transistor.

11. A solid-state imaging device comprising:

a floating diffusion layer which is formed on a surface portion of a semiconductor substrate to receive and store signal charges transferred from an adjacent CCD;

a reset drain formed on the surface portion of the semiconductor substrate to oppose said floating diffusion layer through a channel region;

a reset gate electrode which is formed on said channel region through an insulating film, and electrically connects said floating diffusion layer to said reset drain through said channel region upon application of a reset pulse to transfer the signal charges stored in said floating diffusion layer to said reset drain; and

a reset voltage setting circuit for setting a voltage of the reset pulse to be applied to said reset gate electrode,

wherein said reset voltage setting circuit has a resistive element and a depletion-type MOS transistor series-connected between one end to which a predetermined voltage is applied and the other end which is grounded, and a node for connecting said resistive element to said depletion-type MOS transistor, the node is connected to a reset voltage application electrode, a channel region of said depletion-type MOS transistor being provided by the same process as that for said channel region of a depletion-type reset transistor including said floating diffusion layer, and reset drain, and said reset gate electrode.

12. A device according to claim 11, wherein said reset voltage setting circuit sets a voltage of the reset pulse within a saturation region of said depletion-type MOS transistor included in said reset voltage setting circuit.

13. A device according to claim 11, wherein said reset voltage setting circuit includes said depletion-type MOS transistor manufactured by the same process as that for a depletion-type reset transistor constituted by said floating diffusion layer, said channel region, said reset drain, and said reset gate electrode, so that an amount of change in impurity concentration of said channel region of said reset transistor due to variations in manufacturing process is substantially the same as an amount of change in impurity concentration of said channel region of said depletion-type transistor included in said reset voltage setting circuit, and when the impurity concentration of said channel region of said reset transistor changes owing to variations in manufacturing process, the voltage of the reset pulse set by said reset voltage setting circuit changes to cancel out the change in impurity concentration.

14. A device according to claim 11, wherein said resistive element comprises a diffused resistor.

15. A device according to claim 11, wherein said resistive element comprises an enhancement-type MOS transistor.

16. A solid-state imaging device comprising:

a floating diffusion layer which is formed on a surface portion of a semiconductor substrate to receive and store signal charges transferred from an adjacent CCD;

a charge detecting section for detecting the signal charges stored in said floating diffusion layer and outputting a detection signal;

a reset drain formed on the surface portion of the semiconductor substrate to oppose said floating diffusion layer through a channel region;

a reset gate electrode which is formed on said channel region through an insulating film, and electrically connects said floating diffusion layer to said reset drain through said channel region upon application of a reset pulse to transfer the signal charges stored in said floating diffusion layer to said reset drain; and

a voltage applying section, having an output terminal connected to said reset drain, for outputting a predetermined voltage and applying the voltage to said reset drain and

a resistance-type voltage dividing unit having one end connected to the output terminal of said voltage applying section, the other end which is grounded, a resistive element and a depletion-type MOS transistor series-connected between said one end and said other end, and a node for connecting said resistive element to said depletion-type MOS transistor, said node being connected to said reset gate electrode,

wherein a channel region of said depletion-type MOS transistor is provided by the same process as that for said channel region of a depletion-type reset transistor including said floating diffusion layer, and reset drain, and said reset gate electrode.

17. A device according to claim 16, wherein said resistance-type voltage dividing unit sets a voltage of a reset pulse to be applied to said reset gate electrode within a saturation region of said depletion-type MOS transistor included in said resistance-type voltage dividing unit.

18. A device according to claim 16, wherein said resistive element comprises a diffused resistor.

19. A device according to claim 16, wherein said resistive element comprises an enhancement-type MOS transistor.

20. A device according to claim 16, wherein said channel region included in said resistance-type voltage dividing unit has a substantially same impurity concentration as that of said channel region of said depletion-type reset transistor.