Data pipeline system and data encoding method

• US 6,035,126 A
• Filed: 06/07/1995
• Issued: 03/07/2000
• Est. Priority Date: 06/30/1992
• Status: Expired due to Term

• Current Assignee: Chartoleaux KG LLC (Intellectual Ventures LLC)
• Original Assignee: Discovision Associates (Pioneer Corporation)
• Inventors: Robbins, William Philip, Sotheran, Martin William, Wise, Adrian Philip
• Primary Examiner(s): AN, MENG AI T
• Application Number:
  US08/483,020
• Time in Patent Office: 1,735 Days
• Field of Search: 395/800, 395/375, 395/377, 395/800.29, 395/308, 395/309, 364/231.8, 364/241.8, 364/240.1, 364/DIG. 1
• US Class Current: 712/29
• CPC Class Codes: G06F 12/0207 with multidimensional access, e.g. row/column, matrix
• CPC Class Codes: G06F 12/04 Addressing variable-length words or parts of words
• CPC Class Codes: G06F 12/0607 Interleaved addressing
• CPC Class Codes: G06F 13/16 for access to memory bus G06F13/28 takes precedence
• CPC Class Codes: G06F 13/1673 using buffers
• CPC Class Codes: G06F 13/1689 Synchronisation and timing concerns synchronisation on a memory bus G06F13/4234
• CPC Class Codes: G06F 13/28 using burst mode transfer, e.g. direct memory access DMA, cycle steal G06F13/32 takes precedence
• CPC Class Codes: G06F 9/3867 using instruction pipelines
• CPC Class Codes: G06F 9/4494 data driven
• CPC Class Codes: H04N 19/13 Adaptive entropy coding, e.g. adaptive variable length coding [AVLC] or context adaptive binary arithmetic coding [CABAC]
• CPC Class Codes: H04N 19/42 characterised by implementation details or hardware specially adapted for video compression or decompression, e.g. dedicated software implementation H04N19/635 takes precedence
• CPC Class Codes: H04N 19/423 characterised by memory arrangements H04N19/433 takes precedence
• CPC Class Codes: H04N 19/61 in combination with predictive coding
• CPC Class Codes: H04N 19/91 Entropy coding, e.g. variable length coding [VLC] or arithmetic coding

Abstract

A multi-standard video decompression apparatus has a plurality of stages interconnected by a two-wire interface arranged as a pipeline processing machine. Control tokens and DATA Tokens pass over the single two-wire interface for carrying both control and data in token format. A token decode circuit is positioned in certain of the stages for recognizing certain of the tokens as control tokens pertinent to that stage and for passing unrecognized control tokens along the pipeline. Reconfiguration processing circuits are positioned in selected stages and are responsive to a recognized control token for reconfiguring such stage to handle an identified DATA Token. A wide variety of unique supporting subsystem circuitry and processing techniques are disclosed for implementing the system.

Claims

1. In a pipeline system for decoding and decompressing encoded video data the improvement comprising:

a plurality of sequential pipeline stages;

an input data storage device (LDIN) and an output data storage device (LDOUT) in each stage, with the output data storage device of each stage connected to the following input data storage device of the next successive stage; and

each stage including predetermined processing circuitry with an active state, which it enters when data entering said stage has a predetermined activation pattern, and an inactive state, in which said stage passes data to said following stage without processing;

at least one of said stages comprising a state machine having a current state and a previous state, and having means for maintaining said previous state;

wherein said stage is activated upon recognition of said predetermined activation pattern only upon a predetermined transition from said previous state to said current state;

said plurality of processing stages being interconnected by a two-wire interface for conveyance of variable length control and/or data tokens along said pipeline in the form of universal adaptation units for interfacing with all of said stages in said pipeline and interacting with selected stages in said pipeline, said two-wire interface comprising;

a sender, a receiver, and a clock connected to said sender and said receiver, said clock having transitions from a first state to a second state, wherein data is transferred from said sender to said receiver upon a clock transition only when said sender is ready and said receiver is ready, wherein said two-wire interface further comprises;

electrical validation circuitry in at least one processing stage to generate a validation signal for a first state when data stored in said stage is valid and for a second state when data stored in said stage is invalid, said state defining said stage'"'"'s ability to accept data, said validation circuitry including at least one validation storage device to store said validation signal for the corresponding pipeline stage;

an acceptance signal connecting an adjacent pair of processing stages and conveying an acceptance signal indicative of the ability of said successive pipeline stage to load data stored in the preceding pipeline stage; and

enabling circuitry connected to said data storage devices for generating an enabling signal to enable loading of data and validation signals into the respective storage devices, wherein;

said data storage devices include a primary data storage device and a secondary data storage device;

said data is loaded into said respective primary data storage devices and said validation signal is loaded into a respective primary validation storage device at the same time;

data is loaded into said respective primary data storage device when said acceptance signal assumes an enabling state; and

said acceptance signal assumes said enabling state only when the acceptance signal associated with the data storage device of said next successive pipeline stage is in said enabling state or said data in said data storage device of said next successive pipeline stage is invalid;

whereby said processing stages in said pipe-line are afforded enhanced flexibility in configuration and processing.

2. A system according to claim 1, wherein said tokens comprise a plurality of data words and each said data word includes an extension bit which indicates a presence of additional data words therein;

whereby said token is unlimited in length.