Voltage regulator capable of improving system response

• US 6,037,759 A
• Filed: 09/09/1999
• Issued: 03/14/2000
• Est. Priority Date: 09/09/1999
• Status: Expired due to Term

• Current Assignee: United Microelectronics Corporation
• Original Assignee: United Microelectronics Corporation, United Silicon Incorporated
• Inventors: Lu, Hsin-Pang, Chen, Juei-Lung
• Primary Examiner(s): Han, Jessica
• Application Number:
  US09/392,879
• Time in Patent Office: 187 Days
• Field of Search: 323/273, 323/274, 323/275, 323/280, 330/253, 330/260, 330/291
• US Class Current: 323/280
• CPC Class Codes: G05F 1/46 wherein the variable actually regulated by the final control device is dc G05F1/625 takes precedence

Abstract

A voltage regulator capable of improving system response. The voltage regulator includes a feedback circuit and an operational amplifier. The input terminal of the feedback circuit is coupled to an output voltage terminal for attenuating signals coming out of the output terminal. The operational amplifier comprises a pre-amplifier, a clamping circuit and a power amplifier, all serially connected together. The input terminals of the pre-amplifier are respectively coupled to the output terminal of the feedback circuit and an input voltage terminal. The pre-amplifier is a device for amplifying differential voltage between input voltage signals and feedback voltage signals. The clamping circuit is a device for clamping amplified differential voltage from the pre-amplifier between a pre-defined voltage range. The power amplifier is a device for increasing the power of the differential voltage signals. The invention is able to maintain a quick response from the operational amplifier without reducing the frequency bandwidth of the amplifier.

Claims

1. A voltage regulator capable of improving system response, comprising:

a feedback circuit whose input terminal is coupled to an output voltage terminal for attenuating the output signal; and

an operational amplifier, including;

a pre-amplifier whose input terminals are coupled to the output terminal of the feedback circuit and an input voltage terminal, respectively, wherein the pre-amplifier is a device for amplifying the differential voltage between the feedback output voltage signal and the input voltage signal;

a clamping circuit whose input terminal is coupled to the output terminal of the pre-amplifier, wherein the clamping circuit is a device for clamping differential voltage signals between a pre-defined voltage range; and

a power amplifier whose input terminal is coupled to the output terminal of the clamping circuit while the output terminal is coupled to both the input terminal of the feedback circuit and the output voltage terminal, wherein the power amplifier is a device for increasing the power output of differential voltage signals.

2. The voltage regulator of claim 1, wherein the clamping circuit includes:

a signal line having a first terminal and a second terminal such that the first terminal is coupled to the output terminal of the pre-amplifier while the second terminal is coupled to the input terminal of the power amplifier;

a first clamping element having a first terminal connected to a first voltage source VB and a second terminal connected to the signal line such that the first clamping element is able to clamp when a first voltage level is reached; and

a second clamping element having a first terminal connected to a second voltage source VA and a second terminal connected to the signal line such that the second clamping element is able to clamp when a second voltage level is reached,

wherein the clamping circuit is able to clamp signals outside the voltage range set by the first and the second clamping element.

3. The voltage regulator of claim 2, wherein the first clamping element is constructed using m serially connected PMOS transistors and the second clamping element is constructed using n serially connected PMOS transistors, where m and n are integers so that the first and second voltage level are set to VB-mVtp and VA+nVtp, lo respectively, with Vtp representing the threshold voltage of each PMOS transistor.

4. The voltage regulator of claim 2, wherein the first clamping element is constructed using m serially connected NMOS transistors and the second clamping element is constructed using n serially connected NMOS transistors, where m and n are integers.