Synchronized MIMD multi-processing system and method of operation

• US 6,038,584 A
• Filed: 03/15/1993
• Issued: 03/14/2000
• Est. Priority Date: 11/17/1989
• Status: Expired due to Term

• Current Assignee: Texas Instruments, Inc.
• Original Assignee: Texas Instruments, Inc.
• Inventors: Balmer, Keith
• Primary Examiner(s): TOPLU, LUCIEN
• Application Number:
  US08/032,530
• Time in Patent Office: 2,556 Days
• Field of Search: 364/DIG. 1, 364/DIG. 2
• US Class Current: 709/248
• CPC Class Codes: G06F 9/30032 Movement instructions, e.g. MOVE, SHIFT, ROTATE, SHUFFLE
• CPC Class Codes: G06F 9/30036 Instructions to perform operations on packed data, e.g. vector, tile or matrix operations
• CPC Class Codes: G06F 9/30043 LOAD or STORE instructions; Clear instruction
• CPC Class Codes: G06F 9/30076 to perform miscellaneous control operations, e.g. NOP
• CPC Class Codes: G06F 9/30087 Synchronisation or serialisation instructions
• CPC Class Codes: G06F 9/30112 comprising data of variable length
• CPC Class Codes: G06F 9/3013 according to data content, e.g. floating-point registers, address registers
• CPC Class Codes: G06F 9/30145 Instruction analysis, e.g. decoding, instruction word fields
• CPC Class Codes: G06F 9/3016 Decoding the operand specifier, e.g. specifier format
• CPC Class Codes: G06F 9/30167 of immediate specifier, e.g. constants
• CPC Class Codes: G06F 9/30189 according to execution mode, e.g. mode flag
• CPC Class Codes: G06F 9/30192 according to data descriptor, e.g. dynamic data typing
• CPC Class Codes: G06F 9/321 Program or instruction counter, e.g. incrementing
• CPC Class Codes: G06F 9/325 for loops, e.g. loop detection or loop counter
• CPC Class Codes: G06F 9/355 Indexed addressing
• CPC Class Codes: G06F 9/3832 Value prediction for operands; operand history buffers
• CPC Class Codes: G06F 9/3836 Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution
• CPC Class Codes: G06F 9/3851 from multiple instruction streams, e.g. multistreaming
• CPC Class Codes: G06F 9/3885 using a plurality of independent parallel functional units

Abstract

There is disclosed a multi-processor system arranged, in one embodiment, as an image and graphics processor. The processor is structured with several individual processors all having communication links to several memories. The individual processors can, on a cycle by cycle basis, be grouped in any configuration to run in synchronism (but from different instruction streams) with the other processors in that group. More than one such synchronized group can be formed concurrently. A crossbar switch serves to establish the processor memory links and the entire image processor, including the individual processors, the crossbar switch and the memories are contained on a single silicon chip.

Claims

1. A synchronization system comprising:

a synchronization bus having a plurality of bus lines;

a plurality of processors, equal in number to the number of bus lines in said synchronization bus, each processor fetching and executing instructions independently of other processors, each processor including

a program counter register storing an address of a next instruction for fetching said next instruction;

a synchronization register having a plurality of bits equal in number to the number of processors, each bit corresponding to a unique one of said plurality of processors, said synchronization register having stored therein an indication of which if any other of said processors are to be synchronized with said processor,

an okay to synchronize circuit connected to a corresponding line of said synchronization bus for generating an okay to synchronize signal on said corresponding line of said synchronization bus when said processor is ready to fetch a next instruction,

a synchronization logic unit connected to said synchronization bus, said program counter register and said synchronization register for inhibiting the fetching said next instruction by said program counter register until each processor indicated as to be synchronized with said processor has transmitted said okay to synchronize signal via said synchronization bus, thereafter permitting said fetching of said next instruction by said program counter resister,

an execution unit for executing fetched instructions, whereby each processor is synchronized to said other of said processors indicated in said synchronization register on an instruction by instruction basis,

a synchronization flag memory connected to said synchronization control logic having stored therein an indication of whether said processor is in a synchronized mode or in an unsynchronized mode, and

wherein said synchronization logic unit

inhibits the fetching the next instruction by said program counter register until each processor indicated as to be synchronized with said processor has transmitted said okay to synchronize signal via said synchronization bus when said synchronization flag memory indicates said synchronized mode, and

permits the fetching of the next instruction by said program counter register regardless of the status of said synchronization bus and said synchronization register when said synchronization flag memory indicates said unsynchronized mode.

2. The synchronization system as claimed in claim 1, wherein:

each processor further includes

a two input NAND gate having a first input connected to said okay to synchronize circuit for receiving said okay to synchronize signal, a second input connected to said synchronization flag memory, and an output connected to said corresponding line of said synchronization bus,

whereby said okay to synchronize signal is transmitted to said synchronization bus whenever either (a) said okay to synchronize circuit generates said okay to synchronize signal and said synchronization flag memory indicates said synchronized mode, or (b) said synchronization flag memory indicates said unsynchronized mode.

3. The synchronization system as claimed in claim 1, wherein:

each processor further includes

a second instruction responsive circuit for loading an indication of the synchronized mode into said synchronization flag memory in response to execution of a lock instruction, whereby said lock instruction begins said synchronized mode.

4. The synchronization system as claimed in claim 1, wherein:

each processor further includes

a third instruction responsive circuit for loading an indication of the unsynchronized mode into said synchronization flag memory in response to execution of a unlock instruction, whereby said unlock instruction ends said synchronized mode.

5. A synchronization system comprising:

a synchronization bus having a plurality of bus lines;

a plurality of processors, equal in number to the number of bus lines in said synchronization bus, each processor fetching and executing instructions independently of other processors, each processor including

a program counter register storing an address of a next instruction for fetching said next instruction;

a synchronization register having a plurality of bits equal in number to the number of processors, each bit corresponding to a unique one of said plurality of processors, said synchronization register having stored therein an indication of which if any other of said processors are to be synchronized with said processor,

an okay to synchronize circuit connected to a corresponding line of said synchronization bus for generating on said corresponding line of said synchronization bus an okay to synchronize signal when said processor is ready to fetch a next instruction,

a synchronization flag memory having stored therein an indication of whether said processor is in a synchronized mode or in an unsynchronized mode,

a synchronization logic unit connected to said synchronization bus, said program counter register, said synchronization register and said synchronization flag memory, said synchronization logic unit including

means for inhibiting the fetching said next instruction by said program counter register until each processor indicated as to be synchronized with said processor has transmitted said okay to synchronize signal via said synchronization bus when said synchronization flag memory indicates said synchronized mode and thereafter permitting fetching of said next instruction by said program counter register,

means for permitting the fetching of said next instruction by said program counter register regardless of the status of said synchronization bus and said synchronization register when said synchronization flag memory indicates said unsynchronized mode, and

an execution unit for executing fetched instructions, whereby each processor is synchronized to said other of said processors indicated in said synchronization register on an instruction by instruction basis.

6. The synchronization system as claimed in claim 5, wherein:

each processor wherein

said synchronization logic unit includes

a plurality of two input first NAND gates equal in number to the number of processors, each having an output, a first input connected to a line of said synchronization bus connected to said okay to synchronize unit of a corresponding processor and a second input line connected to a bit of said synchronization register corresponding to said corresponding processor, and

a second NAND gate having a plurality of inputs connected to said output of said plurality of first NAND gates and an output generating the output of said synchronization logic unit.

7. The synchronization system as claimed in claim 5, wherein:

each processor further includes

a first instruction responsive circuit for loading an instruction specified set of bits into said synchronization register in response to execution of a synchronization write instruction, whereby said synchronization write instruction specifies said indication, stored in said synchronization register, of which if any other of said processors are to be synchronized with said processor.

8. The synchronization system as claimed in claim 5, wherein:

each processor further includes

a two input NAND gate having a first input connected to said okay to synchronize circuit for receiving said okay to synchronize signal, a second input connected to said synchronization flag memory, and an output connected to said corresponding line of said synchronization bus,

whereby said okay to synchronize signal is transmitted to said synchronization bus whenever either (a) said okay to synchronize circuit generates said okay to synchronize signal and said synchronization flag memory indicates said synchronized mode, of (b) said synchronization flag memory indicates said unsynchronized mode.

9. The synchronization system as claimed in claim 5, wherein:

each processor further includes

a second instruction responsive circuit for loading an indication of the synchronized mode into said synchronization flag memory in response to execution of a lock instruction, whereby said lock instruction begins said synchronized mode, and

a third instruction responsive circuit for loading an indication of the unsynchronized mode into said synchronization flag memory in response to execution of a unlock instruction, whereby said unlock instruction ends said synchronized mode.

10. The method of operating a computer system having a plurality of processors in synchronism, each of the processors independently fetching and executing instructions, said method comprising the steps of:

storing at each processor an indication of a synchronized mode or an unsynchronized mode;

storing at each processor an indication of other processor or processors to which said processor is to be synchronized;

generating at each processor a ready signal when said processor is ready to fetch an instruction;

inhibiting fetching an instruction at each processor until said processor receives said ready signal from all processors to which that processor is to be synchronized according to said stored indication when said processor stores an indication of the synchronized mode and thereafter permitting fetching said instruction at each processor;

permitting fetching an instruction at each processor regardless of the status of the ready signal of other processors when said processor stores an indication of the unsynchronized mode; and

executing fetched instructions at each processor, whereby each processor is synchronized with said other processor or processors according to said stored indication on an instruction by instruction basis.

11. The method as claimed in claim 10, wherein:

said step of storing at each processor an indication of other processor or processors to which the processor is to be synchronized includes specifying the other processor or processors to which the processor is to be synchronized in response to execution of a first instruction by the processor.

12. The method as claimed in claim 11, wherein:

said step of specifying the other processor or processors to which said processor is to be synchronized includes specifying via a first instruction executed by said processor a subset of the other processors to which said processor is to be synchronized, said processor operating asynchronously with respect to other processors not in said subset.

13. The method as claimed in claim 11, wherein:

said step of specifying the other processor or processors to which said processor is to be synchronized includes specifying via a first instruction executed by said processor a plurality of groups of processors to be synchronized with respect to other processors in the same group and operating each group of processors asynchronously with respect to other groups of processors.

14. The method as claimed in claim 10, wherein:

said step of storing at each processor an indication of a synchronized mode or an unsynchronized mode includes storing an indication of the synchronized mode in response to execution of a lock instruction by said processor.

15. The method as claimed in claim 10, wherein:

said step of storing at each processor an indication of a synchronized mode or an unsynchronized mode includes storing an indication of the unsynchronized mode in response to execution of an unlock instruction by said processor.