Method of integrating Ldd implantation for CMOS device fabrication

• US 6,043,533 A
• Filed: 10/06/1997
• Issued: 03/28/2000
• Est. Priority Date: 02/11/1997
• Status: Expired due to Term

• Current Assignee: GlobalFoundries, Inc.
• Original Assignee: Advanced Micro Devices, Inc.
• Inventors: Hause, Fred, Gardner, Mark I., Paiz, Robert
• Primary Examiner(s): MEIER, STEPHEN D
• Application Number:
  US08/944,377
• Time in Patent Office: 904 Days
• Field of Search: 257/336, 257/344
• US Class Current: 257/336
• CPC Class Codes: H01L 21/823807 with a particular manufacturing method of the channel structures, e.g. channel implants, halo or pocket implants, or channel materials
• CPC Class Codes: H01L 21/823814 with a particular manufacturing method of the source or drain structures, e.g. specific source or drain implants or silicided source or drain structures or raised source or drain structures

Abstract

A method of integrating lightly doped drain implantation for complementary metal oxide semiconductor (CMOS) device fabrication includes providing a semiconductor substrate having a p-well region and an n-well region. A patterned gate oxide and gate electrode are formed on each of the p-well region and the n-well region. One of either the p-well region or the n-well region is masked with a patterned photoresist having a prescribed thickness, leaving a non-masked region exposed. Ions are then implanted to form desired p-type lightly doped drain (Pldd) regions in the n-well region, including Pldd regions adjacent to edges of the gate electrode in the n-well region. Lastly, ions are implanted to form desired n-type lightly doped drain (Nldd) regions in the p-well region, including Nldd regions adjacent to edges of the gate electrode in the p-well region, the Pldd and Nldd regions thus being formed with the use of only a single ion implantation masking step. A semiconductor substrate and an integrated circuit are also disclosed.

Claims

1. A semiconductor substrate having lightly doped drain regions formed by a method comprising the steps of:

providing a semiconductor substrate having a p-well region and an n-well region;

forming a patterned gate oxide and gate electrode on each of the p-well region and the n-well region;

masking one of either the p-well region or the n-well region with a patterned photoresist having a prescribed thickness, leaving a non-masked region exposed;

implanting ions to form desired p-type lightly doped drain (Pldd) regions in the n-well region, including Pldd regions adjacent to edges of the gate electrode in the n-well region such that said implantation in the n-well is on the order of 0.1 μ

m or less; and

implanting ions to form desired n-type lightly doped drain (Nldd) regions in the p-well region, including Nldd regions adjacent to edges of the gate electrode in the p-well region, the Pldd and Nldd regions thus being formed with the use of only a single ion implantation masking step.

2. The semiconductor substrate having lightly doped drain regions of claim 1, wherein

said ion implantation masking step includes masking the n-well region and leaving the p-well region exposed,

said step of implanting ions to form desired Pldd regions in the n-well region includes implanting species of ions selected from the group consisting of arsenic (As), phosphorus (Phos), and combinations of As and Phos, and

said step of implanting ions to form desired Nldd regions in the p-well region includes implanting species of ions selected from the group consisting of boron fluoride (BF₂), boron (B), and any molecule containing boron, and

said step of providing the semiconductor substrate further includes providing an isolation region in between the p-well region and the n-well region.

3. The semiconductor substrate having lightly doped drain regions of claim 1, wherein

said step of forming the patterned gate oxide and gate electrode on each of the p-well region and the n-well region includes leaving a photoresist pattern in place above respective gate electrodes, the photoresist pattern having been used in the formation of the respective patterned gate oxide and gate electrode on each of the p-well region and the n-well region, and

the photoresist pattern and the respective patterned gate oxide and gate electrode on the p-well region together include a prescribed total thickness for obtaining a desired deep doping p+ profile in the p-well during said Pldd ion implanting step, the deep doping p+ profile having a shape which substantially tracks a shape of a respective overlaying gate oxide and gate electrode.

4. An integrated circuit having transistor devices fabricated on a semiconductor substrate having lightly doped drain regions, the semiconductor substrate formed by a method comprising the steps of:

providing a semiconductor substrate having a p-well region and an n-well region;

forming a patterned gate oxide and gate electrode on each of the p-well region and the n-well region;

masking one of either the p-well region or the n-well region with a patterned photoresist having a prescribed thickness, leaving a non-masked region exposed;

implanting ions to form desired n-type lightly doped drain (Nldd) regions in the p-well region, including Nldd regions adjacent to edges of the gate electrode in the p-well region, the Pldd and Nldd regions thus being formed with the use of only a single ion implantation masking step.

5. The integrated circuit of claim 4, further comprising:

an NMOS transistor device formed in the p-well region and a PMOS transistor device formed in the p-well region and a PMOS transistor device formed in the n-well region, wherein the NMOS transistor is characterized by a deep doping p+ profile in the p-well which substantially tracks a shape of a respective overlying gate oxide and gate electrode.

6. The integrated circuit of claim 4, wherein

said ion implantation masking step includes masking the n-well region and leaving the p-well region exposed,

said step of implanting ions to form desired Pldd regions in the n-well region includes implanting species of ions selected from the group consisting of arsenic (As), phosphorus (Phos), and combinations of As and Phos, and

said step of implanting ions to form desired Nldd regions in the p-well region includes implanting species of ions selected from the group consisting of boron fluoride (BF₂), boron (B), and any molecule containing boron, and

said step of providing the semiconductor substrate further includes providing an isolation region in between the p-well region and the n-well region.

7. The integrated circuit of claim 4, wherein

said step of forming the patterned gate oxide and gate electrode on each of the p-well region and the n-well region includes leaving a photoresist pattern in place above respective gate electrodes, the photoresist pattern having been used in the formation of the respective patterned gate oxide and gate electrode on each of the p-well region and the n-well region, and

the photoresist pattern and the respective patterned gate oxide and gate electrode on the p-well region together include a prescribed total thickness for obtaining a desired deep doping p+ profile in the p-well during said Pldd ion implanting step, the deep doping p+ profile having a shape which substantially tracks a shape of a respective overlying gate oxide and gate electrode.