Method of integrating Ldd implantation for CMOS device fabrication

  • US 6,043,533 A
  • Filed: 10/06/1997
  • Issued: 03/28/2000
  • Est. Priority Date: 02/11/1997
  • Status: Expired due to Term
First Claim
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1. A semiconductor substrate having lightly doped drain regions formed by a method comprising the steps of:

  • providing a semiconductor substrate having a p-well region and an n-well region;

    forming a patterned gate oxide and gate electrode on each of the p-well region and the n-well region;

    masking one of either the p-well region or the n-well region with a patterned photoresist having a prescribed thickness, leaving a non-masked region exposed;

    implanting ions to form desired p-type lightly doped drain (Pldd) regions in the n-well region, including Pldd regions adjacent to edges of the gate electrode in the n-well region such that said implantation in the n-well is on the order of 0.1 μ

    m or less; and

    implanting ions to form desired n-type lightly doped drain (Nldd) regions in the p-well region, including Nldd regions adjacent to edges of the gate electrode in the p-well region, the Pldd and Nldd regions thus being formed with the use of only a single ion implantation masking step.

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