Selectively sized spacers

• US 6,046,089 A
• Filed: 01/05/1998
• Issued: 04/04/2000
• Est. Priority Date: 01/05/1998
• Status: Expired due to Term

• Current Assignee: Lone Star Silicon Innovations LLC (Tanit Ventures Inc.)
• Original Assignee: Advanced Micro Devices SDN Berhad (Advanced Micro Devices, Inc.)
• Inventors: Gardner, Mark I., Hause, Fred N., May, Charles E.
• Primary Examiner(s): Fahmy, Wael
• Assistant Examiner(s): COLEMAN, WILLIAM D
• Application Number:
  US09/002,727
• Time in Patent Office: 820 Days
• Field of Search: 438/230, 438/303, 438/366, 438/445, 438/595, 438/696, 438/593, 438/279, 438/275, 438/265, 438/330, 257/900, 257/344, 257/345
• US Class Current: 438/303
• CPC Class Codes: H01L 21/31116 by dry-etching
• CPC Class Codes: H01L 29/6659 with both lightly doped source and drain extensions and source and drain self-aligned to the sides of the gate, e.g. lightly doped drain [LDD] MOSFET, double diffused drain [DDD] MOSFET

Abstract

The formation of selectively sized spacers is disclosed. One embodiment comprises a method including four steps. In the first step, at least one spacer for each of a plurality of gates is formed on a substrate, the plurality of gates including a first gate and at least one remaining gate, and each spacer adjacent to an edge of its corresponding gate. In the second step, a mask is applied to the first gate, including the spacers for the first gate. In the third step, the spacers for the remaining gates are etched. In the fourth step, the mask applied to the first gate, including the spacers for the first gate, is removed.

Claims

1. A method for forming a device comprising:

forming at least one spacer adjacent to an edge of each of a plurality of gates on a substrate, the plurality of gates including a first gate and at least one remaining gate;

applying a mask to the first gate, including at least a portion of said at least one spacer for the first gate;

etching and therein sizing said at least one spacer for each of the at least one remaining gate into a geometry that is smaller than the at least one spacer for the first gate;

removing the mask from the first gate; and

applying an ion implantation and forming a highly doped region within the substrate adjacent to the sized at least one spacer.

2. The method of claim 1, wherein applying an ion implantation and forming a highly doped region further includes forming a lightly doped region within the substrate underneath each spacer.

3. The method of claim 2, further comprising applying a rapid thermal anneal (RTA) to cure the ion implantation.

4. The method of claim 3, further comprising forming a metal silicide within the substrate adjacent to each spacer.

6. The method of claim 1, wherein each spacer has a triangular geometry.

7. The method of claim 6, wherein forming at least one spacer comprises using a high-density plasma (HDP) reactor to simultaneously deposit and etch each spacer.

8. The method of claim 6, wherein forming at least one spacer includes anistropically etching each spacer for at least one of the plurality of gates to reduce the triangular geometry of each spacer.

18. The method of claim 1, further including forming each spacer of the first gate and each spacer of the remaining gate using a high-density plasma (HDP) reactor to simultaneously deposit and etch each first spacer and each second spacer.

5. A method for forming a device comprising:

forming at least one spacer adjacent to an edge of each of a plurality of gates on a substrate, the plurality of gates including a first gate and at least one remaining gate;

applying a mask to the first gate, including at least a portion of said at least one spacer for the first gate;

etching and therein sizing said at least one spacer for each of the at least one remaining gate into a geometry that is smaller than the at least one spacer for the first gate;

removing the mask from the first gate; and

applying an ion implantation and forming a highly doped region within the substrate adjacent to the sized at least one spacer; and

prior to forming at least one spacer for each of a plurality of gates on a substrate, applying an ion implantation and forming a lightly doped region within the substrate adjacent to each edge of each gate.

9. A method for forming a device comprising:

forming at least one spacer adjacent to an edge of each of a plurality of gates on a substrate, the plurality of gates including a first gate and at least one remaining gate;

applying a mask to the first gate, including at least a portion of said at least one spacer for the first gate;

etching and therein sizing said at least one spacer for each of the at least one remaining gate into a geometry that is smaller than the at least one spacer for the first gate;

removing the mask from the first gate; and

applying an ion implantation and forming a highly doped region within the substrate adjacent to the sized at least one spacer; and

forming a third gate on the substrate having a spacer of the smaller geometry.

10. The method of claim 9, wherein the smaller geometry is made by applying a mask to the first gate, including the at least one spacer for the first gate, and etching the at least one second spacer for a second gate.

11. The method of claim 10, wherein forming comprises forming a highly doped region within the substrate adjacent to each first spacer and each second spacer.

13. The method of claim 10, wherein forming comprises forming a lightly doped region within the substrate underneath each spacer and each second spacer.

15. The method of claim 10, wherein the first gate has a first channel length extending under the first gate and the at least one spacer, and the remaining gate has a second channel length extending under the remaining gate and the at least one spacer of the remaining gate, such that the second channel length is less than the first channel length.

12. A method for forming a device comprising:

forming at least one spacer adjacent to an edge of each of a plurality of gates on a substrate, the plurality of gates including a first gate and at least one remaining gate;

applying a mask to the first gate, including at least a portion of said at least one spacer for the first gate;

etching and therein sizing said at least one spacer for each of the at least one remaining gate into a geometry that is smaller than the at least one spacer for the first gate;

removing the mask from the first gate; and

applying an ion implantation and forming a highly doped region within the substrate adjacent to the sized at least one spacer; and

forming comprises forming a highly doped region within the substrate adjacent to each first spacer and each second spacer.

14. A method for forming a device comprising:

forming at least one spacer adjacent to an edge of each of a plurality of gates on a substrate, the plurality of gates including a first gate and at least one remaining gate;

applying a mask to the first gate, including at least a portion of said at least one spacer for the first gate;

etching and therein sizing said at least one spacer for each of the at least one remaining gate into a geometry that is smaller than the at least one spacer for the first gate;

removing the mask from the first gate; and

applying an ion implantation and forming a highly doped region within the substrate adjacent to the sized at least one spacer; and

wherein the first gate has a first channel length extending under the first gate and the at least one spacer, and the remaining gate has a second channel length extending under the remaining gate and the at least one spacer of the remaining gate, such that the second channel length is less than the first channel length.

17. The method of claim 14, further including forming each spacer of the first gate and each spacer of the remaining gate, using a high-density plasma (HDP) reactor to simultaneously deposit and etch each first spacer and each second spacer.

16. A method for forming a device comprising:

forming at least one spacer adjacent to an edge of each of a plurality of gates on a substrate, the plurality of gates including a first gate and at least one remaining gate;

applying a mask to the first gate, including at least a portion of said at least one spacer for the first gate;

etching and therein sizing said at least one spacer for each of the at least one remaining gate into a geometry that is smaller than the at least one spacer for the first gate;

removing the mask from the first gate; and

applying an ion implantation and forming a highly doped region within the substrate adjacent to the sized at least one spacer; and

wherein each spacer of the first gate has a first triangular geometry, and each spacer of the remaining gate has a second triangular geometry.