High sensitivity active pixel with electronic shutter

• US 6,046,444 A
• Filed: 12/08/1997
• Issued: 04/04/2000
• Est. Priority Date: 12/08/1997
• Status: Expired due to Term

• Current Assignee: Intel Corporation
• Original Assignee: Intel Corporation
• Inventors: Afghahi, Morteza
• Primary Examiner(s): Lee, John R
• Application Number:
  US08/987,176
• Time in Patent Office: 848 Days
• Field of Search: 250/208.1, 250/214 LS, 250/214 LA, 250/214 A, 250/214 C, 250/214.1, 250/214 R, 348/294, 348/297, 348/248, 348/300, 348/301, 348/302, 348/303, 348/308, 348/311, 348/312, 257/225, 257/231, 257/236, 257/239, 257/290, 257/291, 257/292, 257/294, 257/443, 257/444, 327/94, 377/60, 377/61, 377/62, 377/63
• US Class Current: 250/208.1
• CPC Class Codes: G11C 27/026 associated with an amplifier G11C27/028 takes precedence
• CPC Class Codes: G11C 7/005 with combined beam-and individual cell access
• CPC Class Codes: H01L 27/14609 Pixel-elements with integrated switching, control, storage or amplification elements scanning details of imagers (circuitry of solid-state image sensors H04N25/00); circuitry of imagers H04N25/70
• CPC Class Codes: H04N 25/53 Control of the integration time
• CPC Class Codes: H04N 25/57 Control of the dynamic range
• CPC Class Codes: H04N 25/771 comprising storage means other than floating diffusion

Abstract

A high sensitivity active pixel for use in MOS image sensor circuits. The pixel circuit design allows the use of digital MOS fabrication processes to be used in implementing a pixel circuit having greater sensitivity (allowing increased frame rate) and greater noise immunity than certain prior art pixels. The novel pixel features a source follower configured amplifier, such as a single MOS FET, coupled between a photodetector and a storage capacitor. A light-generated signal from the photodetector is used to control the charge placed in the storage capacitor in order to develop a capture voltage. In a particular embodiment, an n-channel source follower and a p-channel output stage are combined in the pixel to make the overall transfer function of the pixel more linear and distortion-free. In particular, the pixel transfer function becomes more linear for weak light-generated signals, whereas with conventional pixels, the pixel output signals are often distorted and even suppressed when the light-generated signal is weak. The novel pixel circuit may find particular use in a portable digital image capture system such as a digital camera.

Claims

1. A circuit, comprising:

photodetecting circuitry providing an original signal;

a first FET having a gate, a drain, and a source, the first FET to provide an output current in response to receiving the original signal at the gate and a first control signal at the drain; and

storage circuitry coupled to the source for receiving the output current.

2. A circuit as in claim 1 wherein the FET is n-channel.

3. A circuit as in claim 1 wherein the photodetecting circuitry includes a reset FET coupled to a photodiode, the reset FET being coupled to receive a second control signal that is the complement of the first control signal and that provides a current for resetting the photodiode.

4. A circuit as in claim 1 wherein the storage circuitry comprises a capacitor coupled to a common supply node at one end and for receiving the output current at another end.

5. A circuit as in claim 1 further comprising

an output stage having a second FET of which a gate is coupled to the storage circuitry and a source is coupled to a switch, the switch to selectively provide a current representative of the original signal.

6. A circuit as in 5 wherein said second FET is n-channel, the circuit further comprising

a compensation circuit coupled between the gate of the second FET and a select input of the switch to raise the voltage at the gate of the second FET in response to a select signal being asserted at the select input.

7. A circuit as in claim 6 wherein the storage circuitry includes a first capacitor and the compensation circuit includes a second capacitor, the first and second capacitors being coupled to the gate of the second FET, the capacitance values of said first and second capacitors being selected such that the voltage at the gate is raised by at least one V_T in response to the second capacitor receiving the select signal.

8. An imaging system, comprising:

an optical system for being exposed to incident light;

an image sensor coupled to the optical system to receive the incident light, the sensor having a plurality of pixels, each pixel having

photodetecting circuitry providing an original signal representative of the incident light,

an FET having a gate, a drain, and a source, the FET to provide an output current in response to receiving the original signal at the gate and a first control signal at the drain,

storage circuitry coupled to the source for receiving the output current and in response providing an exposed voltage representative of the incident light, and

analog-to-digital conversion circuitry coupled to the sensor for converting analog signals related to the exposed voltage in each pixel into digital signals representing raw image data.

9. A system as in claim 8 further comprising

means for digital signal and image processing, said means generating captured image data in response to receiving the digital signals;

and

an output interface for transferring the captured image data to an image processing system separate from the imaging system.

10. A system as in claim 9 further comprising display means for displaying the captured image data.

11. A system as in claim 9 further comprising an LCD to display the captured image data.

12. A system as in claim 9 further comprising a storage means for receiving and storing the captured image data.

13. A system as in claim 9 further comprising a removable memory card to store the captured image data.

14. A system as in claim 8 further comprising logic circuitry for compressing and scaling the raw image data.

15. A system as in claim 8 further comprising:

a controller for managing the operations of the imaging system in response to instructions stored as firmware.

16. A system as in claim 15 wherein the controller generates the first control signal, a photodetector reset signal, and a pixel address signal for controlling operation of each pixel in the image sensor.

17. An image sensor comprising:

a plurality of bitlines; and

a plurality of pixels arranged as rows and columns to form an array, each pixel in one of the columns having photodetecting circuitry to provide an original signal representative of incident light detected in an integration interval, a first FET having a signal input, a control input, and signal output to provide an output current in response to receiving the original signal at the signal input and a first control signal being asserted at the control input upon completion of the integration interval, first capacitor coupled to the signal output for receiving the output current, and output stage coupled between the capacitor and a respective one of the plurality of bitlines to selectively buffer a voltage of the capacitor onto said respective one of the bitlines.

18. The image sensor of claim 17 wherein the first FET is n-channel.

19. The image sensor of claim 17 wherein the photodetecting circuitry includes a reset FET coupled to a photodiode, the reset FET being coupled to receive a second control signal that is the complement of the first control signal and that provides a current for resetting the photodiode.

20. The image sensor of claim 17 wherein each pixel further comprises a second FET having a gate coupled to the capacitor and a source coupled to a switch, the switch to selectively provide a current representative of the original signal.

21. The image sensor of claim 20 wherein the second FET is n-channel and each pixel further comprises a compensation circuit coupled between the gate of the second FET and a select input of the switch to raise the voltage at the gate of the second FET in response to a select signal being asserted at the select input.

22. The image sensor of claim 20 wherein the compensation circuit includes a second capacitor, the first and second capacitors being coupled to the gate of the second FET, the capacitance values of said first and second capacitors being selected such that the voltage at the gate is raised by at least one V_T in response to the second capacitor receiving the select signal.