Body driven SOI-MOS field effect transistor

• US 6,049,110 A
• Filed: 06/26/1997
• Issued: 04/11/2000
• Est. Priority Date: 06/26/1996
• Status: Expired due to Term

• Current Assignee: Renesas Electronics Corporation
• Original Assignee: NEC Corporation
• Inventors: Koh, Risho
• Primary Examiner(s): Abraham, Fetsum
• Application Number:
  US08/883,442
• Time in Patent Office: 1,020 Days
• Field of Search: 257/280, 257/281, 257/282, 257/471-472, 257/347-364, 438/364
• US Class Current: 257/347
• CPC Class Codes: H01L 29/66772 Monocristalline silicon transistors on insulating substrates, e.g. quartz substrates H01L29/66666 takes precedence; thin film FinFETs H01L29/66795
• CPC Class Codes: H01L 29/785 having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/78648 arranged on opposing sides of the channel

Abstract

In a body driven SOIMOSFET, a semiconductor layer extends over the insulator and comprises a first conductivity type high impurity concentration diffusion layer, a low impurity concentration region and another first conductivity type high impurity concentration diffusion layer which are in this order connected with each other. A second conductivity type high impurity concentration semiconductor layer is formed in contact with a top of the low impurity concentration region. A bottom electrode is formed within the insulation layer so that the bottom electrode is surrounded by the insulation layer. The bottom electrode is positioned under the low impurity concentration region and being separated by the insulation layer from the low impurity concentration region. It is important that the bottom electrode does not extend under the first conductivity high impurity concentration regions.

Claims

1. A semiconductor device comprising:

a bottom electrode region;

an insulation layer extending on at least a top surface of said bottom electrode region;

a first semiconductor region of a first conductivity type formed over a first area of said insulation layer, said first semiconductor region having a first impurity concentration;

a second semiconductor region formed over a second area of said insulation layer, one side of said second semiconductor region being in contact directly with said first semiconductor region, said second semiconductor region having a second impurity concentration which is lower than said first impurity concentration, said second semiconductor region being one of a first conductivity type extrinsic semiconductor, a second conductivity type extrinsic semiconductor and an intrinsic semiconductor;

a third semiconductor region of said first conductivity type formed over a third area of said insulation layer, said third semiconductor region being in contact directly with an opposite side of said second semiconductor region, said third semiconductor region having a third impurity concentration which is higher than said second impurity concentration; and

a top electrode region formed in contact directly with a top surface of said second semiconductor region, said top electrode region being applied with a voltage signal,

wherein said bottom electrode region is applied with a bottom gate voltage of an opposite polarity to said first conductivity type, and

wherein ε

1/d1>

ε

2/d2, where ε

1 is a first dielectric constant of said second semiconductor region, d1 is a distance between a top of a depletion layer located within said second semiconductor region and a highest carrier concentration portion of a channel layer extending upward from a bottom interface of said second semiconductor region, ε

2 is a second dielectric constant of said insulation layer, and d2 is a thickness of said insulation layer.

2. The semiconductor device as claimed in claim 1, wherein said bottom electrode region comprises an impurity-doped semiconductor layer.

3. The semiconductor device as claimed in claim 1, wherein said bottom electrode region comprises an impurity-doped semiconductor substrate.

4. The semiconductor device as claimed in claim 1, wherein said bottom electrode region comprises a metal layer.

5. The semiconductor device as claimed in claim 1, wherein said bottom electrode region comprises a metal silicide layer.

6. The semiconductor device as claimed in claim 1, wherein said bottom electrode region comprises an alloy layer.

7. The semiconductor device as claimed in claim 1, wherein said bottom electrode region comprises a conductive material.

8. The semiconductor device as claimed in claim 1, wherein said top electrode region comprises a second conductivity type semiconductor which has a fourth impurity concentration being higher than said second impurity concentration of said second semiconductor region.

9. The semiconductor device as claimed in claim 8, wherein a part of said top electrode region comprises a conductive material which is higher in conductivity than and is different in material from said second conductivity type semiconductor.

10. The semiconductor device as claimed in claim 9, wherein said conductive material comprises a metal.

11. The semiconductor device as claimed in claim 9, wherein said conductive material comprises an alloy.

12. The semiconductor device as claimed in claim 9, wherein said conductive material comprises a metal silicide.

13. The semiconductor device as claimed in claim 9, wherein said conductive material comprises a semiconductor.

14. The semiconductor device as claimed in claim 9, wherein said conductive material extends over a top surface of said second conductivity type semiconductor.

15. The semiconductor device as claimed in claim 9, wherein said conductive material extends not only over a top surface but also on side walls of said second conductivity type semiconductor.

16. The semiconductor device as claimed in claim 8, wherein said second conductivity type semiconductor has a wider band gap than those of said first, second and third semiconductor regions.

17. The semiconductor device as claimed in claim 1, wherein said top electrode region comprises a metal.

18. The semiconductor device as claimed in claim 1, wherein said top electrode region comprises an alloy.

19. The semiconductor device as claimed in claim 1, wherein said top electrode region comprises a metal silicide.

20. The semiconductor device as claimed in claim 1, wherein said second semiconductor region is of said first conductivity type.

21. The semiconductor device as claimed in claim 1, wherein said second semiconductor or region is of a second conductivity type.

22. The semiconductor device as claimed in claim 1, wherein said second semiconductor region comprises an intrinsic semiconductor.

23. The semiconductor device as claimed in claim 1, wherein said second semiconductor region has a top surface level which is equal to said first and third semiconductor regions.

24. The semiconductor device as claimed in claim 1, wherein said second semiconductor region has a top surface level which is higher than said first and third semiconductor regions.

25. The semiconductor device as claimed in claim 24, further comprising an insulation film extending over said first and third semiconductor regions and said insulation film being in contact directly with side walls of a higher level portion of said second semiconductor region than said first and third semiconductor regions.

26. The semiconductor device as claimed in claim 1, wherein said first conductivity type is n-type and said second semiconductor region comprises:

a bottom layer being in contact directly with said insulation layer, and said bottom layer having a first conduction band edge; and

a top layer of the same conductivity type as said bottom layer, said top layer extending over said bottom layer and being in contact directly with said top electrode region, and said top layer having a second conduction band edge which lies in vacuum at a higher level than that of said first conduction band edge.

27. The semiconductor device as claimed in claim 1, wherein said first conductivity type is p-type and said second semiconductor region comprises:

a bottom layer being in contact directly with said insulation layer, and said bottom layer having a first valence band edge; and

a top layer of the same conductivity type as said bottom layer, said top layer extending over said bottom layer and being in contact directly with said top electrode region, and said top layer having a second valence band edge which lies in vacuum at a lower level than that of said first valence band edge.

28. The semiconductor device as claimed in claim 1, wherein at least a part of said second semiconductor region comprises a narrow band gap region.

29. The semiconductor device as claimed in claim 1, wherein at least a part of said second semiconductor region comprises an Si--Ge amorphous region.

30. The semiconductor device as claimed in claim 1, wherein at least a part of said second semiconductor region comprises a Ge region.

31. The semiconductor device as claimed in claim 1, wherein said second semiconductor region comprises:

a bottom layer comprising an intrinsic semiconductor, and said bottom layer being in contact directly with said insulation layer; and

a top layer of a second conductivity type extending over said bottom layer and being in contact directly with said top electrode region.

32. The semiconductor device as claimed in claim 1, wherein said second semiconductor region comprises:

a bottom layer comprising an intrinsic semiconductor, and said bottom layer being in contact directly with said insulation layer; and

a top layer of said first conductivity type extending over said bottom layer and being in contact directly with said top electrode region.

33. The semiconductor device as claimed in claim 1, wherein said insulation layer has a region having charges of an opposite polarity to said first conductivity type and extending at least under said second semiconductor region.

34. The semiconductor device as claimed in claim 33, wherein said bottom gate voltage is of an opposite polarity to said first conductivity type.

35. The semiconductor device as claimed in claim 33, wherein said bottom gate voltage is zero.

36. The semiconductor device as claimed in claim 1, wherein said insulation layer includes a ferroelectric layer being so polarized that a top interface of said ferroelectric layer has an opposite polarity to said first conductivity type and a bottom interface of said ferroelectric layer has the same polarity as said first conductivity type.

37. The semiconductor device as claimed in claim 36, wherein said bottom gate voltage is of an opposite polarity to said first conductivity type.

38. The semiconductor device as claimed in claim 36, wherein said bottom gate voltage is zero.

39. The semiconductor device as claimed in claim 1, wherein said insulation layer extends over said top surface of said bottom electrode region.

40. The semiconductor device as claimed in claim 39, further comprising a floating gate electrode being positioned between said second semiconductor region and said bottom electrode region, said floating gate electrode being surrounded by said insulation layer and separated from said bottom electrode region and said second semiconductor region by said insulation layer.

41. The semiconductor device as claimed in claim 1, wherein said insulation layer extends on entire surfaces of said bottom electrode region so that said bottom electrode region is surrounded by said insulation layer.

42. The semiconductor device as claimed in claim 41, further comprising a floating gate electrode being positioned between said second semiconductor region and said bottom electrode region, said floating gate electrode being surrounded by said insulation layer and separated from said bottom electrode region and said second semiconductor region by said insulation layer.

43. The semiconductor device as claimed in claim 1, wherein said top electrode region is vertically and horizontally off-set from said first and third semiconductor regions, and wherein said insulation layer extends on entire surfaces of said bottom electrode region so that said bottom electrode region is surrounded by said insulation layer.

44. The semiconductor device as claimed in claim 1, wherein said second semiconductor region is of said first conductivity type and said first conductivity type is n-type provided that said bottom gate voltage is of an opposite polarity to said first conductivity type.

45. The semiconductor device as claimed in claim 1, wherein said second semiconductor region is of said first conductivity type and said first conductivity type is n-type provided that said bottom gate voltage is zero.

46. A semiconductor device comprising:

an insulation layer;

a first semiconductor region of a first conductivity type formed over a first area of said insulation layer, said first semiconductor region having a first impurity concentration;

a second semiconductor region formed over a second area of said insulation layer, one side of said second semiconductor region being in contact directly with said first semiconductor region, said second semiconductor region having a second impurity concentration which is lower than said first impurity concentration, said second semiconductor region being one of a first conductivity type extrinsic semiconductor, a second conductivity type extrinsic semiconductor and an intrinsic semiconductor;

a third semiconductor region of said first conductivity type formed over a third area of said insulation layer, said third semiconductor region being in contact directly with an opposite side of said second semiconductor region, said third semiconductor region having a third impurity concentration which is higher than said second impurity concentration; and

a top electrode region formed in contact directly with a top surface of said second semiconductor region, said top electrode region being applied with a voltage signal,

wherein said insulation layer has a region having charges of an opposite polarity to said first conductivity type and extending at least under said second semiconductor region.

47. The semiconductor device as claimed in claim 46, wherein said top electrode region comprises a second conductivity type semiconductor which has a fourth impurity concentration being higher than said second impurity concentration of said second semiconductor region.

48. The semiconductor device as claimed in claim 47, wherein a part of said top electrode region comprises a conductive material which is higher in conductivity than and is different in material from said second conductivity type semiconductor.

49. The semiconductor device as claimed in claim 48, wherein said conductive material comprises a metal.

50. The semiconductor device as claimed in claim 48, wherein said conductive material comprises an alloy.

51. The semiconductor device as claimed in claim 48, wherein said conductive material comprises a metal suicide.

52. The semiconductor device as claimed in claim 48, wherein said conductive material comprises a semiconductor.

53. The semiconductor device as claimed in claim 48, wherein said conductive material extends over a top surface of said second conductivity type semiconductor.

54. The semiconductor device as claimed in claim 48, wherein said conductive material extends not only over a top surface but also on side walls of said second conductivity type semiconductor.

55. The semiconductor device as claimed in claim 47, wherein said second conductivity type semiconductor has a wider band gap than those of said first, second and third semiconductor regions.

56. The semiconductor device as claimed in claim 46, wherein said top electrode region comprises a metal.

57. The semiconductor device as claimed in claim 46, wherein said top electrode region comprises an alloy.

58. The semiconductor device as claimed in claim 46, wherein said top electrode region comprises a metal silicide.

59. The semiconductor device as claimed in claim 46, wherein said second semiconductor region is of said first conductivity type.

60. The semiconductor device as claimed in claim 46, wherein said second semiconductor region has a top surface level which is equal to said first and third semiconductor regions.

61. The semiconductor device as claimed in claim 46, wherein said second semiconductor region has a top surface level which is higher than said first and third semiconductor regions.

62. The semiconductor device as claimed in claim 61, further comprising an insulation film extending over said first and third semiconductor regions and said insulation film being in contact directly with side walls of a higher level portion of said second semiconductor region than said first and third semiconductor regions.

63. The semiconductor device as claimed in claim 46, wherein said first conductivity type is n-type and said second semiconductor region comprises:

a bottom layer being in contact directly with said insulation layer, and said bottom layer having a first conduction band edge; and

a top layer of the same conductivity type as said bottom layer, said top layer extending over said bottom layer and being in contact directly with said top electrode region, and said top layer having a second conduction band edge which lies in vacuum at a higher level than that of said first conduction band edge.

64. The semiconductor device as claimed in claim 46, wherein at least a part of said second semiconductor region comprises a narrow band gap region.

65. The semiconductor device as claimed in claim 46, wherein at least a part of said second semiconductor region comprises an Si--Ge amorphous region.

66. The semiconductor device as claimed in claim 46, wherein at least a part of said second semiconductor region comprises a Ge region.

67. The semiconductor device as claimed in claim 46, wherein said second conductivity type charge region comprises a charge containing region.

68. The semiconductor device as claimed in claim 46, wherein said second conductivity type charge region comprises a top interface of a ferroelectric layer included in said insulation layer provided that said ferroelectric layer is so polarized that said top interface has an opposite polarity to said first conductivity type and a bottom interface of said ferroelectric layer has the same polarity as said first conductivity type.

69. A semiconductor device comprising:

a bottom electrode region;

an insulation layer extending on at least a top surface of said bottom electrode region;

a first semiconductor region of a first conductivity type formed over a first area of said insulation layer, said first semiconductor region having a first impurity concentration;

a second semiconductor region formed over a second area of said insulation layer, one side of said second semiconductor region being in contact directly with said first semiconductor region, said second semiconductor region having a second impurity concentration which is lower than said first impurity concentration, said second semiconductor region being one of a first conductivity type extrinsic semiconductor, a second conductivity type extrinsic semiconductor and an intrinsic semiconductor;

a third semiconductor region of said first conductivity type formed over a third area of said insulation layer, said third semiconductor region being in contact directly with an opposite side of said second semiconductor region, said third semiconductor region having a third impurity concentration which is higher than said second impurity concentration; and

a top electrode region formed in contact directly with a top surface of said second semiconductor region, said top electrode region being applied with a voltage signal,

wherein said bottom electrode region is applied with a bottom gate voltage of an opposite polarity to said first conductivity type, and

wherein Ccg>

Ccb, where Ccg is a first capacitance between said top electrode and a highest impurity concentration portion of an inversion region caused in said second semiconductor region, and Ccb is a first capacitance between said top electrode and said highest carrier concentration portion of said inversion region.

70. The semiconductor device as claimed in claim 69, wherein said bottom electrode region comprises an impurity doped semiconductor layer.

71. The semiconductor device as claimed in claim 69, wherein said bottom electrode region comprises an impurity-doped semiconductor substrate.

72. The semiconductor device as claimed in claim 69, wherein said bottom electrode region comprises a metal layer.

73. The semiconductor device as claimed in claim 69, wherein said bottom electrode region comprises a metal silicide layer.

74. The semiconductor device as claimed in claim 69, wherein said bottom electrode region comprises an alloy layer.

75. The semiconductor device as claimed in claim 69, wherein said bottom electrode region comprises a conductive material.

76. The semiconductor device as claimed in claim 69, wherein said top electrode region comprises a second conductivity type semiconductor which has a fourth impurity concentration being higher than said second impurity concentration of said second semiconductor region.

77. The semiconductor device as claimed in claim 76, wherein a part of said top electrode region comprises a conductive material which is higher in conductivity than and is different in material from said second conductivity type semiconductor.

78. The semiconductor device as claimed in claim 77, wherein said conductive material comprises a metal.

79. The semiconductor device as claimed in claim 77, wherein said conductive material comprises an alloy.

80. The semiconductor device as claimed in claim 77, wherein said conductive material comprises a metal silicide.

81. The semiconductor device as claimed in claim 77, wherein said conductive material comprises a semiconductor.

82. The semiconductor device as claimed in claim 77, wherein said conductive material extends over a top surface of said second conductivity type semiconductor.

83. The semiconductor device as claimed in claim 77, wherein said conductive material extends not only over a top surface but also on side walls of said second conductivity type semiconductor.

84. The semiconductor device as claimed in claim 76, wherein said second conductivity type semiconductor has a wider band gap than those of said first, second and third semiconductor regions.

85. The semiconductor device as claimed in claim 69, wherein said top electrode region comprises a metal.

86. The semiconductor device as claimed in claim 69, wherein said top electrode region comprises an alloy.

87. The semiconductor device as claimed in claim 69, wherein said top electrode region comprises a metal silicide.

88. The semiconductor device as claimed in claim 69, wherein said second semiconductor region is of said first conductivity type.

89. The semiconductor device as claimed in claim 69, wherein said second semiconductor region is of a second conductivity type.

90. The semiconductor device as claimed in claim 69, wherein said second semiconductor region comprises an intrinsic semiconductor.

91. The semiconductor device as claimed in claim 69, wherein said second semiconductor region has a top surface level which is equal to said first and third semiconductor regions.

92. The semiconductor device as claimed in claim 69, wherein said second semiconductor region has a top surface level which is higher than said first and third semiconductor regions.

93. The semiconductor device as claimed in claim 92, further comprising an insulation film extending over said first and third semiconductor regions and said insulation film being in contact directly with side walls of a higher level portion of said second semiconductor region than said first and third semiconductor regions.

94. The semiconductor device as claimed in claim 69, wherein said first conductivity type is n-type and said second semiconductor region comprises:

a bottom layer being in contact directly with said insulation layer, and said bottom layer comprising a semiconductor having a first conduction band edge; and

a top layer of the same conductivity type as said bottom layer, said top layer extending over said bottom layer and being in contact directly with said top electrode region, and said top layer comprising a semiconductor having a second conduction band edge which lies in vacuum at a higher level than that of said first conduction band edge.

95. The semiconductor device as claimed in claim 69, wherein said first conductivity type is p-type and said second semiconductor region comprises:

a bottom layer being in contact directly with said insulation layer, and said bottom layer comprising a semiconductor having a first valence band edge; and

a top layer of the same conductivity type as said bottom layer, said top layer extending over said bottom layer and being in contact directly with said top electrode region, and said top layer comprising a semiconductor having a second valence band edge which lies in vacuum at a lower level than that of said first valence band edge.

96. The semiconductor device as claimed in claim 69, wherein at least a part of said second semiconductor region comprises a narrow band gap region.

97. The semiconductor device as claimed in claim 69, wherein at least a part of said second semiconductor region comprises an Si--Ge amorphous region.

98. The semiconductor device as claimed in claim 69, wherein at least a part of said second semiconductor region comprises a Ge region.

99. The semiconductor device as claimed in claim 69, wherein said second semiconductor region comprises:

a bottom layer comprising an intrinsic semiconductor, and said bottom layer being in contact directly with said insulation layer; and

a top layer of a second conductivity type extending over said bottom layer and being in contact directly with said top electrode region.

100. The semiconductor device as claimed in claim 69, wherein said second semiconductor region comprises:

a bottom layer comprising an intrinsic semiconductor, and said bottom layer being in contact directly with said insulation layer; and

a top layer of said first conductivity type extending over said bottom layer and being in contact directly with said top electrode region.

101. The semiconductor device as claimed in claim 69, wherein said insulation layer has a region having charges of an opposite polarity to said first conductivity type and extending at least under said second semiconductor region.

102. The semiconductor device as claimed in claim 101, wherein said bottom gate voltage is of an opposite polarity to said first conductivity type.

103. The semiconductor device as claimed in claim 101, wherein said bottom gate voltage is zero.

104. The semiconductor device as claimed in claim 69, wherein said insulation layer includes a ferroelectric layer extending under said second conductivity type ion containing region, said ferroelectric layer being so polarized that a top interface of said ferroelectric layer has an opposite polarity to said first conductivity type and a bottom interface of said ferroelectric layer has the same polarity as said first conductivity type.

105. The semiconductor device as claimed in claim 104, wherein said bottom gate voltage is of an opposite polarity to said first conductivity type.

106. The semiconductor device as claimed in claim 104, wherein said bottom gate voltage is zero.

107. The semiconductor device as claimed in claim 69, wherein said insulation layer extends over said top surface of said bottom electrode region.

108. The semiconductor device as claimed in claim 107, further comprising a floating gate electrode being positioned between said second semiconductor region and said bottom electrode region, said floating gate electrode being surrounded by said insulation layer and separated from said bottom electrode region and said second semiconductor region by said insulation layer.

109. The semiconductor device as claimed in claim 69, wherein said insulation layer extends on entire surfaces of said bottom electrode region so that said bottom electrode region is surrounded by said insulation layer.

110. The semiconductor device as claimed in claim 109, further comprising a floating gate electrode being positioned between said second semiconductor region and said bottom electrode region, said floating gate electrode being surrounded by said insulation layer and separated from said bottom electrode region and said second semiconductor region by said insulation layer.

111. The semiconductor device as claimed in claim 69, wherein said top electrode region is vertically and horizontally off-set from said first and third semiconductor regions, and wherein said insulation layer extends on entire surfaces of said bottom electrode region so that said bottom electrode region is surrounded by said insulation layer.

112. The semiconductor device as claimed in claim 69, wherein said second semiconductor region is of said first conductivity type and said first conductivity type is n-type provided that said bottom gate voltage is of an opposite polarity to said first conductivity type.

113. The semiconductor device as claimed in claim 69, wherein said second semiconductor region is of said first conductivity type and said first conductivity type is n-type provided that said bottom gate voltage is zero.

114. A semiconductor device comprising:

an insulation layer;

a first semiconductor region of a first conductivity type formed over a first area of said insulation layer, said first semiconductor region having a first impurity concentration;

a second semiconductor region formed over a second area of said insulation layer, one side of said second semiconductor region being in contact directly with said first semiconductor region, said second semiconductor region having a second impurity concentration which is lower than said first impurity concentration;

a third semiconductor region of said first conductivity type formed over a third area of said insulation layer, said third semiconductor region being in contact directly with an opposite side of said second semiconductor region, said third semiconductor region having a third impurity concentration which is higher than said second impurity concentration; and

a top electrode region formed in contact directly with a top surface of said second semiconductor region, said top electrode region being applied with a voltage signal,

wherein said insulation layer has a region having charges of an opposite polarity to said first conductivity type and extending at least under said second semiconductor region, and

wherein Ccg>

Ccb, where Ccg is a first capacitance between said top electrode and a highest impurity concentration portion of an inversion region caused in said second semiconductor region, and Ccb is a first capacitance as a coupling capacitance between (i) a channel extending upward from a bottom interface of said second semiconductor region and (ii) said first and third semiconductor regions through said insulation layer.

115. The semiconductor device as claimed in claim 114, wherein said top electrode region comprises a second conductivity type semiconductor which has a fourth impurity concentration being higher than said second impurity concentration of said second semiconductor region.

116. The semiconductor device as claimed in claim 115, wherein a part of said top electrode region comprises a conductive material which is higher in conductivity than and is different in material from said second conductivity type semiconductor.

117. The semiconductor device as claimed in claim 116, wherein said conductive material comprises a metal.

118. The semiconductor device as claimed in claim 116, wherein said conductive material comprises an alloy.

119. The semiconductor device as claimed in claim 116, wherein said conductive material comprises a metal silicide.

120. The semiconductor device as claimed in claim 116, wherein said conductive material comprises a semiconductor.

121. The semiconductor device as claimed in claim 116, wherein said conductive material extends over a top surface of said second conductivity type semiconductor.

122. The semiconductor device as claimed in claim 116, wherein said conductive material extends not only over a top surface but also on side walls of said second conductivity type semiconductor.

123. The semiconductor device as claimed in claim 115, wherein said second conductivity type semiconductor has a wider band gap than those of said first, second and third semiconductor regions.

124. The semiconductor device as claimed in claim 114, wherein said top electrode region comprises a metal.

125. The semiconductor device as claimed in claim 114, wherein said top electrode region comprises an alloy.

126. The semiconductor device as claimed in claim 114, wherein said top electrode region comprises a metal silicide.

127. The semiconductor device as claimed in claim 114, wherein said second semiconductor region is of said first conductivity type.

128. The semiconductor device as claimed in claim 114, wherein said second semiconductor region has a top surface level which is equal to said first and third semiconductor regions.

129. The semiconductor device as claimed in claim 114, wherein said second semiconductor region has a top surface level which is higher than said first and third semiconductor regions.

130. The semiconductor device as claimed in claim 129, further comprising an insulation film extending over said first and third semiconductor regions and said insulation film being in contact directly with side walls of a higher level portion of said second semiconductor region than said first and third semiconductor regions.

131. The semiconductor device as claimed in claim 114, wherein said first conductivity type is n-type and said second semiconductor region comprises:

a bottom layer being in contact directly with said insulation layer, and said bottom layer comprising a semiconductor having a first conduction band edge; and

a top layer of the same conductivity type as said bottom layer, said top layer extending over said bottom layer and being in contact directly with said top electrode region, and said top layer comprising a semiconductor having a second conduction band edge which lies at a higher level than that of said first conduction band edge.

132. The semiconductor device as claimed in claim 114, wherein at least a part of said second semiconductor region comprises a narrow band gap region.

133. The semiconductor device as claimed in claim 114, wherein at least a part of said second semiconductor region comprises an Si--Ge amorphous region.

134. The semiconductor device as claimed in claim 114, wherein at least a part of said second semiconductor region comprises a Ge region.

135. The semiconductor device as claimed in claim 114, wherein said second conductivity type charge region comprises a charge containing region.

136. The semiconductor device as claimed in claim 114, wherein said second conductivity type charge region comprises a top interface of a ferroelectric layer included in said insulation layer provided that said ferroelectric layer is so polarized that said top interface has an opposite polarity to said first conductivity type and a bottom interface of said ferroelectric layer has the same polarity as said first conductivity type.

137. A semiconductor device comprising:

an insulation layer;

a semiconductor layer extending over said insulator and comprising a first conductivity type high impurity concentration diffusion layer, a low impurity concentration region and another first conductivity type high impurity concentration diffusion layer which are in this order connected with each other;

a second conductivity type high impurity concentration semiconductor layer formed in contact with a top of said low impurity concentration region, said second semiconductor region being one of a first conductivity type extrinsic semiconductor, a second conductivity type extrinsic semiconductor and an intrinsic semiconductor; and

a bottom electrode formed under said insulation layer.

138. The semiconductor device as claimed in claim 137, wherein said low impurity concentration region comprises a region being doped with a first conductivity type impurity at a low concentration.

139. The semiconductor device as claimed in claim 137, wherein said low impurity concentration region comprises a region being doped with a second conductivity type impurity at a low concentration.

140. The semiconductor device as claimed in claim 139, wherein said low impurity concentration region comprises an intrinsic semiconductor.

141. The semiconductor device as claimed in claim 140, wherein said bottom electrode comprises a conductive material.

142. The semiconductor device as claimed in claim 141, wherein said conductive material is a metal.

143. The semiconductor device as claimed in claim 141, wherein said conductive material is a metal silicide.

144. The semiconductor device as claimed in claim 141, wherein said bottom electrode comprises a semiconductor.

145. The semiconductor device as claimed in claim 137, wherein said low impurity concentration region is of the first conductivity type and an upper portion of said low impurity concentration region has a higher impurity concentration than a lower portion of said low impurity concentration region.

146. The semiconductor device as claimed in claim 137, wherein a conductive electrode is buried in said insulation layer and a potential of said conductive electrode is varied to change a threshold voltage at which a channel is formed in said monocrystal semiconductor.

147. The semiconductor device as claimed in claim 137, wherein at least a part of said bottom electrode at positions facing to said first conductivity type high impurity concentration regions has a larger distance from said semiconductor layer than that at positions facing to said low impurity concentration region.

148. A semiconductor device comprising:

an insulation layer;

a semiconductor layer extending over said insulator and comprising a first conductivity type high impurity concentration diffusion layer, a low impurity concentration region and another first conductivity type high impurity concentration diffusion layer which are in this order connected with each other;

a second conductivity type high impurity concentration semiconductor layer formed in contact with a top of said low impurity concentration region, said second semiconductor region being one of a first conductivity type extrinsic semiconductor, a second conductivity type extrinsic semiconductor and an intrinsic semiconductor; and

a bottom electrode formed within said insulation layer so that the bottom electrode is surrounded by said insulation layer, said bottom electrode being positioned under said low impurity concentration region and being separated by said insulation layer from said low impurity concentration region,

wherein said bottom electrode has a width which is equal to or nearly equal to a width of said low impurity concentration region so that edges of said bottom electrode are positioned to just or almost correspond in plane view to edges of the low impurity concentration region.

149. A semiconductor device comprising:

an insulation layer;

a semiconductor layer extending over said insulator and comprising a first conductivity type high impurity concentration diffusion layer, a low impurity concentration region and another first conductivity type high impurity concentration diffusion layer which are in this order connected with each other;

a second conductivity type high impurity concentration semiconductor layer formed in contact with a top of said low impurity concentration region, said second semiconductor region being one of a first conductivity type extrinsic semiconductor, a second conductivity type extrinsic semiconductor and an intrinsic semiconductor; and

a bottom electrode formed within said insulation layer so that the bottom electrode is surrounded by said insulation layer, said bottom electrode being positioned under said low impurity concentration region and being separated by said insulation layer from said low impurity concentration region,

wherein said bottom electrode does not extend under said first conductivity high impurity concentration regions.