Failure analyzer with distributed data processing network and method used therein

• US 6,049,895 A
• Filed: 12/08/1997
• Issued: 04/11/2000
• Est. Priority Date: 12/09/1996
• Status: Expired due to Fees

• Current Assignee: NEC Corporation
• Original Assignee: NEC Corporation
• Inventors: Sugimoto, Masaaki
• Primary Examiner(s): Sheikh, Ayaz R.
• Assistant Examiner(s): PANCHOLI, JIGAR K
• Application Number:
  US08/985,918
• Time in Patent Office: 855 Days
• Field of Search: 709/203, 714/25-46
• US Class Current: 714/46
• CPC Class Codes: G01R 31/318505 Test of Modular systems, e.g. Wafers, MCM's
• CPC Class Codes: G01R 31/318511 Wafer Test
• CPC Class Codes: G01R 31/31935 Storing data, e.g. failure memory

Abstract

A failure analyzer has an electric characteristic inspection system for producing pieces of electric test data information for integrated circuit devices fabricated on a semiconductor wafer, a visual inspection system for producing pieces of appearance test data information for the semiconductor wafer and a data analyzing system for producing a failure analysis report from the pieces of electric test data information and the pieces of appearance test data information, and the data analyzing system is implemented by using a client-server network technology so as to increase a data processing capability depending upon the amount of data to be analyzed.

Claims

1. A failure analyzer for analyzing pieces of test data information having pieces of appearance test data information and pieces of electric test data information, comprising:

a test system including a visual inspection sub-system carrying out an appearance test for a semiconductor wafer so as to produce said pieces of appearance test data information, and an electric characteristic inspection sub-system carrying out electric tests for integrated circuit devices fabricated on said semiconductor wafer for producing said pieces of electric test data information; and

a data analyzing system connected to said test system for analyzing said pieces of test data information, and implemented by using a client-server network technology.

2. The failure analyzer as set forth in claim 1, in which said data analyzing system includes

a general analyzer producing a piece of failure analysis report information from pieces of local analysis data information,

a plurality of local analyzers for producing said pieces of local analysis data information,

a data distributor distributing said pieces of test data information to said plurality of local analysis data information, and

a communicating network connected between said general analyzer, said plurality of local analyzers and said data distributor.

3. The failure analyzer as set forth in claim 2, in which said data distributor produces a small piece of test data information for one of said plurality of local analyzers with a small data processing capability and a large piece of test data information for another of said plurality of local analyzer with a large data processing capability.

4. The failure analyzer as set forth in claim 2, in which the number of said plurality of local analyzers is changeable.

5. A method for analyzing pieces of data information obtained from an integrated circuit fabricated on a semiconductor wafer, comprising the steps of:

a) carrying out electric tests for electric components of said integrated circuit and an appearance test for an area of said semiconductor wafer so as to produce pieces of electric test data information each representative of a first diagnosis or a second diagnosis of one of said electric components and a piece of appearance test data information representative of a diagnosis of said area, and

b) making said pieces of electric test data information representative of either first or second diagnosis depending upon the ratio of the electric components diagnosed to be said first diagnosis to the electric components diagnosed to be said second diagnosis.

6. The method as set forth in claim 5, in which said electric components are memory cells, and said first diagnosis and said second diagnosis are defective and non-defective.

7. A method for analyzing pieces of data information obtained from an integrated circuit fabricated on a semiconductor wafer, comprising the steps of:

a) carrying out electric tests for electric components of said integrated circuit and an appearance test for an area of said semiconductor wafer so as to produce pieces of electric test data information each representative of a first diagnosis or a second diagnosis of one of said electric components and a piece of appearance test data information representative of a diagnosis of said area; and

b) making said pieces of electric test data information representative of either first or second diagnosis depending upon the ratio of the electric components diagnosed to be said first diagnosis to the electric components diagnosed to be said second diagnosis, wherein a high level-analysis is carried out by assigning coordinates on said semiconductor wafer to each electric defect, as represented in said electric test data information, and results of said high level-analysis are used to determine a pattern of said electric defects.

8. A method as recited in claim 7, wherein said electric components are memory cells, and said first diagnosis and said second diagnosis are defective and non-defective, respectively.