Fault tolerant data bus

• US 6,052,753 A
• Filed: 01/20/1998
• Issued: 04/18/2000
• Est. Priority Date: 01/21/1997
• Status: Expired due to Term

• Current Assignee: Alliedsignal Inc.
• Original Assignee: Alliedsignal Inc.
• Inventors: Doerenberg, Frank, McElroy, Jim
• Primary Examiner(s): AUVE, GLENN ALLEN
• Application Number:
  US09/009,463
• Time in Patent Office: 819 Days
• Field of Search: 710/126, 710/129, 710/117, 710/124, 710/25, 710/29, 710/30, 710/45
• US Class Current: 710/305
• CPC Class Codes: G01S 13/91 for traffic control G01S13/93 takes precedence
• CPC Class Codes: G01S 13/933 of aircraft or spacecraft
• CPC Class Codes: G01S 13/935 for terrain-avoidance
• CPC Class Codes: G01S 13/95 for meteorological use
• CPC Class Codes: G05D 1/0077 using redundant signals or controls
• CPC Class Codes: G08G 5/0095 Aspects of air-traffic control not provided for in the other subgroups of this main group
• CPC Class Codes: Y02A 90/10 Information and communication technologies [ICT] supporting adaptation to climate change, e.g. for weather forecasting or climate simulation

Abstract

A fault tolerant bus architecture and protocol for use in applications wherein data must be handled with a high degree of integrity and in a fault tolerant manner. As applied to an integrated flight hazard avoidance system, the system is constructed of two or more microprocessor-driven modules that generate data, two independent bus interface controllers per module, and an inter-module backplane data bus that links each module. The system allows comparison of identical data from multiple sources. If invalid data is detected, the system either passes the correct data copy or generates a system fault message. The bus architecture utilizes a distributed synchronization protocol, and does not require a master synchronization source.

Claims

1. A data bus system comprising:

a processor having an application memory;

a bus interface controller operatively connected to said processor and said application memory;

a data bus including at least one data line wherein data is transmitted in a plurality of time frames wherein each of said time frames is divided into a plurality of time slots; and

a time table operatively connected to said bus interface controller for mapping a plurality of said time slots into a data transmission channel wherein said channel in each of said time frames is assigned to said bus interface controller for transmission of data from said bus interface controller to said channel on said data bus.

2. The system of claim 1 additionally including a space table operatively connected to said bus interface controller for mapping said channel into a predetermined location in said application memory.

3. The system of claim 2 additionally including a memory management means for causing said processor to load said space table with a plurality of application addresses defining said predetermined location in said application memory relating to applications to be executed by said processor.

4. A data bus system comprising:

a plurality of nodes each including a processor having an application memory;

a first bus interface controller for each of said nodes operatively connected to said processor and said application memory for that node;

a data bus including at least one data line wherein data is transmitted in a plurality of time frames wherein each of said time frames is divided into a plurality of time slots;

a time table operatively connected to each of said first bus interface controllers for mapping a plurality of said time slots in each of said frames into a data transmission channel wherein each of said channels is assigned to a predetermined one of said nodes for transmission of data to and from said application memory in said predetermined node through said first bus interface controller to and from said channel on said data bus; and

a space table operatively connected to each of said first bus interface controllers for mapping said channel assigned to that node into a predetermined data location in said application memory for that node.

5. The system of claim 4 wherein all said time tables are identical.

6. The system of claim 5 wherein said space tables contain a plurality of addresses for said predetermined data locations in that node'"'"'s application memory for an application to be executed by said processor in that node.

7. The system of claim 4 wherein at least one of said nodes includes a second bus interface controller operatively connected to said processor, said application memory and said first bus interface controller in that node and wherein said second bus interface controller is operatively connected to an additional one of said time tables and an additional one of said space tables for that node.

8. The system of claim 7 wherein said bus includes at least two data lines and said first and said second bus interface controller are connected to seperate ones of said data lines and wherein said first bus interface controller obtains data from said application memory to be transmitted to said bus transmits said data to said second bus interface means and wherein said first and said second bus interface controllers have enable means for permitting each of said bus controllers to transmit said data to said seperate bus lines.

9. The system of claim 7 wherein said bus includes at least two data lines and said first and said second bus interface controllers connected to each of said data lines and wherein said first and second bus interface controllers obtain data from said bus lines, perform error detection and data comparisons on the data received from each of said data lines and said first bus interface controller writes said data to said application memory if said error detection and data comparisons indicate valid data.

10. A data bus system comprising:

a data bus including at least one data line wherein data is transmitted in a plurality of time frames wherein each of said time frames is divided into a plurality of time slots;

a plurality of nodes each including a first and a second processor for executing application programs each having an independent application memory and an independent clock wherein the data resulting from said programs is transmitted to said application memories by each of said processors;

a pair of bus interface controllers located in each of said nodes and individually connected one to each of said application memories in each of said nodes including means for receiving said data from said data bus wherein said bus interface controllers in each node are connected by a data exchange line;

a time table operatively connected to each of said bus interface controllers for mapping a plurality of said time slots in each of said frames into a data transmission channel wherein each of said channels is assigned to a predetermined one of said nodes for transmission of data to and from said application memory through its associated bus interface controller to and from said channel on said data bus;

comparison means located in said bus interface controllers for exchanging said data received from each said application memory over said data exchange line and comparing said data in each of said bus interface controllers; and

transmission means associated with each of said bus interface controllers and responsive to said time table for transmitting said data to said data lines if said comparison means indicates said data is equivalent.

11. The system of claim 10 wherein said first and second processors execute the same application independently and transmit said data to said first and second application memories.

12. The system of claim 11 wherein each of said bus interface controllers includes wait means for delaying said comparison of said data a predetermined amount of time until the other bus interface controller receives said data from said application memory.

13. A data bus system comprising:

a data bus including at least one data line wherein data is transmitted in a plurality of time frames wherein each of said time frames is divided into a plurality of time slots;

a plurality of nodes each including a first and a second processor for executing different application programs independently wherein each of said first and second processors is operatively connected to a separate independent application memory and a separate independent clock wherein the data resulting from said programs is transmitted to said application memories by each of said processors;

a pair of bus interface controllers located in each of said nodes and individually connected one to each of said application memories in each of said nodes including means for transmitting said data to and receiving said data from said data bus; and

a time table operatively connected to each of said bus interface controllers for mapping a plurality of said time slots in each of said frames into a data transmission channel wherein each of said channels is assigned to a predetermined one of said nodes for transmission of data to and from said application memory through its associated bus interface controller to and from said channel on said data bus.

14. A method of transmitting data over a data bus between a plurality of nodes wherein each of the nodes includes at least one processor, comprising the steps of:

transmitting the data on the data bus in a plurality of time slots divided into a plurality of channels wherein each of said channels is assigned to one of the nodes;

selectively receiving a first portion of said data in a first of said channels in a first of said nodes having two of the processors by a pair of bus interface controllers located in said first node wherein each of said bus interface controllers includes a time table defining said first channel containing said first portion of said data; and

transferring said first portion of said data from said bus interface controllers to a pair of application memories each associated with the processors in said first node wherein a pair of space tables, each associated with one of said bus interface controllers defines the location in said application memories into which said first portion of said data is to be transferred.

15. The method of claim 14 including the step of comparing said first portion of said data in said bus interface controllers prior to transferring it to said application memories.

16. The method of claim 14 wherein said first portion of said data in said channel includes address labels for specific locations in said application memories.

17. The method of claim 14 additionally including the steps of:

executing the same application program in both said of said processors in said first node;

transferring a second portion of data resulting from said application program to said application memories in locations specified in said space tables;

transferring said second portion of data from said application memories to said bus interface controllers;

comparing said second portion of data in one of said bus interface controllers; and

if said second portion of data is the same in each of said bus interface controllers, then transferring said second portion of data to a second channel in the data bus as specified by said time tables.

18. The method of claim 17 wherein each of said processors in said first node has its own clock and executes said application program independently.

19. The method of claim 18 including the step of causing each of said bus interface controllers to wait a predetermined time to receive said second portion of data from said application memories and if said second portion of data is not received within said predetermined time, said data is not compared and and is not transferred to the data bus.

20. A method of transmitting data over a data bus between a plurality of nodes wherein each of the nodes includes at least one processor, comprising the steps of:

transmitting the data on the data bus in a plurality of time slots divided into a plurality of channels wherein each of said channels is assigned to one of the nodes;

selectively receiving a first portion of said data in a first of said channels in a first of said nodes having one of the processors by a pair of bus interface controllers located in said first node wherein each of said bus interface controllers includes a time table defining said first channel containing said first portion of said data;

transferring said first portion of said data from said bus interface controllers to an application memory associated with the processor in said first node wherein a pair of space tables, each associated with one of said bus interface controllers defines the location in said application memories into which said first portion of said data is to be transferred; and

comparing said first portion of said data in said bus interface controllers prior to transferring it to said application memory.