Temperature measurement and compensation scheme

• US 6,055,489 A
• Filed: 04/15/1997
• Issued: 04/25/2000
• Est. Priority Date: 04/15/1997
• Status: Expired due to Term

• Current Assignee: Intel Corporation
• Original Assignee: Intel Corporation
• Inventors: Beatty, Timothy S., Fletcher, Thomas D., McAllister, Christopher P.
• Primary Examiner(s): Hoff, Marc S.
• Assistant Examiner(s): Bui, Bryan
• Application Number:
  US08/843,327
• Time in Patent Office: 1,106 Days
• Field of Search: 702/99, 702/117, 702/130, 702/132, 374/178, 374/181, 374/182, 374/183, 374/101, 374/173, 327/67, 327/512
• US Class Current: 702/130
• CPC Class Codes: G01K 3/005 Circuits arrangements for indicating a predetermined temperature fire detection G08B17/00
• CPC Class Codes: G01K 7/01 using semiconducting elements having PN junctions G01K7/02, G01K7/16, G01K7/30 take precedence

Abstract

An integrated circuit includes: a comparator coupled in a configuration to compare two voltages. One of the two voltages includes a semiconductor junction voltage drop. The other of the two voltages includes a voltage signal, X V_t, where V_t is a thermal voltage and X includes a selected signal value, which modulates the thermal voltage. The configuration includes a feedback path to vary X until X V_t approximately equals the voltage including the semiconductor junction voltage drop.

Claims

1. An integrated circuit comprising:

a comparator being coupled in a configuration to compare two voltage signals, one of the two voltage signals comprising a semiconductor junction voltage of a semiconductor device, another of the two voltage signals comprising a voltage signal X V_t, where V_t comprises the thermal voltage and X comprises a selected signal value modulating the thermal voltage;

the comparator configuration including a feedback path to vary X until X V_t approximately equals the semiconductor junction voltage.

2. The integrated circuit of claim 1, wherein the comparator configuration includes an electrical path to produce the voltage signal XV_t at least in part from a bias current supplied along said electrical path, the bias current being derived from a bandgap circuit.

3. The integrated circuit of claim 2, wherein said bandgap circuit comprises a bandgap circuit to produce said bias current without generating a bandgap voltage.

4. The integrated circuit of claim 3, wherein said electrical path comprises a selected electrical path through a resistor network.

5. The integrated circuit of claim 4, wherein said feedback path to vary X comprising a successive approximation circuit to sample an output signal of said comparator and produce the output signal of said successive approximation circuit, based at least in part, upon the output signal of said comparator, wherein said selected electrical path through a resistor network is based, at least in part, upon the output signal of said successive approximation circuit.

6. The integrated circuit of claim 5, and further comprising a look-up table responsive to the output signal of said successive approximation circuit, said look-up table storing clock pulse timing adjustments.

7. The integrated circuit of claim 1, wherein the semiconductor junction voltage comprises a P-N junction voltage of the semiconductor device.

8. An integrated circuit circuit comprising:

a timer circuit to produce for a specified charging time a clock pulse count to compare with a reference clock pulse count adjusted by a temperature compensation clock pulse timing adjustment;

a circuit configuration to measure temperature; and

a look-up table storing clock pulse timing adjustments, said look-up table responsive to an output signal of said circuit configuration to measure temperature.

9. The integrated circuit of claim 8, wherein said specified charging time comprises the elapsed time to charge a capacitor with an approximately constant current from a first predetermined reference voltage to a second predetermined reference voltage.

10. The integrated circuit of claim 8, wherein said circuit configuration to measure temperature includes a bandgap circuit to produce a bias current proportional to the thermal voltage, V_t.

11. The integrated circuit of claim 10, wherein said circuit configuration to measure temperature has an operating voltage below a bandgap voltage.

12. The integrated circuit of claim 10, wherein said bandgap circuit to produce a bias current does not produce a bandgap voltage.

13. The integrated circuit of claim 8, wherein the output signal of said current configuration to measure temperature comprises a memory address location and said look-up table comprises a read-only-memory (ROM).

14. The integrated circuit of claim 8, wherein said look-up table stores temperature compensation clock pulse timing adjustments in the form of a percentage of the reference clock pulse count.

15. The integrated circuit of claim 8, wherein said look-up table stores temperature compensation clock pulse timing adjustments in the form of signal values to be added to the reference clock pulse count.

16. A method of testing the frequency of a clock on an integrated circuit comprising:

producing a clock pulse count for a predetermined electrical charging time;

measuring the temperature of the integrated circuit;

adjusting a reference clock pulse count based, at least in part, upon the temperature measured; and

comparing the clock pulse count produced for the predetermined electrical charging time with the reference clock pulse count adjusted for the measured temperature.

17. The method of claim 16, wherein producing a clock pulse count for a predetermined electrical charging time comprises producing a clock pulse count for the time it takes a capacitor to charge from a first reference voltage to a second reference voltage.

18. The method of claim 16, wherein measuring the temperature of the integrated circuit comprises:

comparing two voltages having known temperature profiles, the two voltages capable of being approximately equalized by a unique value of a circuit component parameter at a distinctly resolvable temperature of the integrated circuit; and

changing the circuit component parameter relating the two voltages until the two voltages are approximately equal.

19. The method of claim 18, wherein one of the two voltages comprises the semiconductor junction voltage of a semiconductor device, and another of the two voltages comprises a voltage proportional to the thermal voltage, V_t.

20. The method of claim 19, wherein changing the circuit component parameter relating the two voltages until the two voltages are approximately equal comprises changing a resistance.

21. The method of claim 20, wherein the step of adjusting the reference clock pulse count comprises adding a clock pulse adjustment corresponding to the resistance that approximately equalizes the two voltages.

22. The method of claim 20, wherein the step at adjusting the reference clock pulse count includes using a clock pulse adjustment that comprises a percentage of the reference clock pulse count.

23. An integrated circuit comprising:

a first transistor coupled in a configuration to operate as a voltage-controlled substantially constant current source;

a second transistor coupled to the first transistor, said second transistor biased to provide a cascode bias with respect to said first transistor;

the bias on said second transistor being proportional to the control voltage of said first transistor at a voltage level just sufficient to maintain said first transistor in saturation.

24. The integrated circuit of claim 23, wherein said transistors comprise metal-oxide semiconductor (MOS) transistors.

25. The integrated circuit of claim 23, wherein said first transistor is coupled in a bandgap circuit, the control voltage being coupled in a feedback loop of said bandgap circuit so that the substantially constant current comprises a bandgap circuit bias current.

26. The integrated circuit of claim 25, wherein the bias on said second transistor proportional to the control voltage of said first transistor is produced using a plurality of transistors coupled in a configuration to operate as current mirrors and relatively sized to provide a control voltage level just sufficient to maintain said first transistor in saturation.