Computer system having a common display memory and main memory

• US 6,057,862 A
• Filed: 07/01/1997
• Issued: 05/02/2000
• Est. Priority Date: 07/01/1997
• Status: Expired due to Term

• Current Assignee: Foothills IP LLC
• Original Assignee: MemTrax LLC
• Inventors: Margulis, Neal
• Primary Examiner(s): Chauhan, Ulka J.
• Application Number:
  US08/886,237
• Time in Patent Office: 1,036 Days
• Field of Search: 345/501-506, 345/520, 345/521, 345/507, 345/186, 345/510, 345/509, 345/515, 345/516, 345/508, 345/511, 345/512, 345/518, 345/203, 395/309, 395/311, 395/312, 711/1, 711/5, 711/6, 711/147-153, 711/167, 711/168, 711/170, 711/173, 710/100, 710/129-132
• US Class Current: 345/535
• CPC Class Codes: G06F 13/1605 based on arbitration arbitration in handling access to a common bus or bus system G06F13/36
• CPC Class Codes: G09G 2360/121 using a cache memory
• CPC Class Codes: G09G 2360/122 Tiling
• CPC Class Codes: G09G 2360/125 using unified memory architecture [UMA]
• CPC Class Codes: G09G 3/003 to produce spatial visual effects
• CPC Class Codes: G09G 5/001 Arbitration of resources in a display system, e.g. control of access to frame buffer by video controller and/or main processor
• CPC Class Codes: G09G 5/363 Graphics controllers
• CPC Class Codes: G09G 5/393 Arrangements for updating the contents of the bit-mapped memory
• CPC Class Codes: H04N 19/46 Embedding additional information in the video signal during the compression process H04N19/517, H04N19/68, H04N19/70 take precedence
• CPC Class Codes: H04N 19/527 Global motion vector estimation
• CPC Class Codes: H04N 19/61 in combination with predictive coding

Abstract

A memory architecture having one or more shared high-bandwidth memory subsystems each coupled over a plurality of buses to a display subsystem, a central processing unit (CPU) subsystem, input/output (I/O) buses and other controllers. The display subsystem receives data from the high-speed shared memory for processing various video and graphics data types for display refresh. Additional buffers and caches are used for the subsystems to further optimize system performance. The display refresh path includes processing of the data from the memory subsystem for output to the display where the data enters the shared memory from an I/O subsystem or from the CPU subsystem.

Claims

1. A computer system comprising:

a common memory architecture including,

a display memory,

a main memory, and

a plurality of memory subsystems, each memory subsystem coupled to one of a plurality of dedicated memory channels;

a memory channel data switch and controller (DSC) unit coupled through said plurality of memory channels to each of said memory subsystems;

an arbitration and control (A&

C) unit for allocating access through said memory channel DSC unit to said memory subsystems;

a central processing unit (CPU) subsystem controller unit for providing first signals through a first data bus and through an address and control bus to said memory channel DSC unit and to said A&

C unit, respectively; and

a graphics/drawing and display (GDD) subsystem for providing second signals through a second data bus and through said address and control bus to said memory channel DSC unit and to said A&

C unit, respectively;

wherein said memory channel DSC unit provides said GDD subsystem with access to any one of said plurality of memory subsystems and provides said CPU subsystem controller unit with concurrent access to any other of said plurality of memory subsystems.

2. The computer system of claim 1 further comprising:

a peripheral bus and input/output control unit;

a plurality of peripheral subsystems coupled to said peripheral bus and input/output control unit; and

a data bus which is distinct from said first data bus and from said second data bus, which is coupled to said peripheral bus and input/output control unit, and which provides access for each of said plurality of peripheral subsystems to any of said memory subsystems.

3. The computer system of claim 2 wherein each of said plurality of peripheral subsystems is selected from the group consisting of a peripheral component interface (PCI), an accelerated graphics port (AGP), an input/output (I/O) bridge and a high speed serial I/O bus.

4. The computer system of claim 2 wherein said memory channel DSC unit, said A&

C unit, said CPU subsystem controller unit, said GDD subsystem and said peripheral bus and input/output control unit together comprise an integrated enhanced system controller.

5. The computer system of claim 1 wherein said A&

C unit produces third signals for receipt by said CPU subsystem controller unit and by said GDD subsystem.

6. The computer system of claim 5 wherein said A&

C unit provides fourth signals to said memory channel DSC unit, and said DSC unit allocates said memory subsystem with a priority preference and a designated maximum latency tolerance to said CPU subsystem controller unit and said GDD subsystem.

7. The computer system of claim 1 wherein said memory channel DSC unit and said A&

C unit comprise an integrated memory channel DSC unit.

8. The computer system of claim 1 wherein said GDD subsystem writes data into any of said plurality of memory subsystems.

9. The computer system of claim 1 wherein said GDD subsystem comprises a display subsystem and a graphics drawing subsystem.

10. The computer system of claim 1 wherein said GDD unit includes a partial drawing buffer and a graphics engine, said graphics engine writes display output data to said partial drawing buffer, and said partial drawing buffer transfers at least a portion of the display output to one of said memory subsystems for use during subsequent display updates.

11. The computer system of claim 10 wherein said partial drawing buffer is a complete drawing buffer and said portion of the display output data is the complete display output data.

12. The computer system of claim 1 wherein said GDD unit includes:

a graphics controller to perform 3D graphics functions; and

a texture cache from which said graphics controller can fetch data.

13. The computer system of claim 1 wherein said GDD subsystem is constructed to utilize display refresh data without storing a second copy of the display refresh data or using a CPU.

14. The computer system of claim 1 wherein said memory channel DSC unit includes:

a plurality of controls, each control corresponding to a respective one of the plurality of memory subsystems;

an arbiter for taking requests from multiple processor or peripheral subsystems; and

a memory data path through which one of the plurality of memory subsystems provides memory data to a processor or peripheral subsystem while said path provides for access of another memory subsystem by any additional processor or peripheral subsystem.

15. A method for organizing a computer system having a common display memory and main memory, comprising:

providing a plurality of memory subsystems within said common display memory and main memory, each memory subsystem having a dedicated memory channel;

providing a memory channel data switch and controller (DSC) unit coupled to each of said memory subsystems through said dedicated memory channels; and

providing a plurality of processor and/or peripheral subsystems including a graphics/drawing and display (GDD) subsystem and a central processing unit (CPU) subsystem controller unit, each of said processor and/or peripheral subsystems coupled to said memory channel data switch and controller unit;

wherein said GDD subsystem can access any one of said plurality of memory subsystems and said CPU subsystem controller unit can concurrently access any other of said plurality of memory subsystems through said memory channel DSC unit.