Memory circuits, systems, and methods with cells using back bias to control the threshold voltage of one or more corresponding cell transistors

• US 6,061,267 A
• Filed: 09/28/1998
• Issued: 05/09/2000
• Est. Priority Date: 09/28/1998
• Status: Expired due to Term

• Current Assignee: Texas Instruments, Inc.
• Original Assignee: Texas Instruments, Inc.
• Inventors: Houston, Theodore W.
• Primary Examiner(s): Nelms, David
• Assistant Examiner(s): NGUYEN, VAN THU T
• Application Number:
  US09/161,903
• Time in Patent Office: 589 Days
• Field of Search: 365/154, 365/226, 365/189.09
• US Class Current: 365/154
• CPC Class Codes: G11C 11/404 with one charge-transfer gate, e.g. MOS transistor, per cell
• CPC Class Codes: G11C 11/4085 Word line control circuits, e.g. word line drivers, - boosters, - pull-up, - pull-down, - precharge
• CPC Class Codes: G11C 11/412 using field-effect transistors only

Abstract

A memory configuration (20). The memory configuration comprises a plurality of memory cells (SCI1, SCI2, SCI3) arranged in a plurality of rows and columns. The memory configuration also comprises a plurality of wordlines (WL₀ -WL_N). Each of the plurality of wordlines corresponds to one of the plurality of rows and is operable during a period to provide a gate bias to select the row corresponding to the wordline such that other rows in the plurality of rows are non-selected rows during the period. In addition, each of the plurality of memory cells comprises at least one transistor (e.g., AT3) coupled to receive a back bias. The memory configuration also comprises circuitry for providing a first back bias operable to cause only the at least one transistor in each of the memory cells in the selected row (e.g., WL₀) to have a first threshold voltage, and circuitry for providing a second back bias operable to cause the at least one transistor in each of the memory cells in at least some of the non-selected rows to have a second threshold voltage. The first threshold voltage is different than the second threshold voltage.

Claims

1. A memory configuration, comprising:

a memory array comprising a plurality of memory cells arranged in a plurality of rows and columns;

a plurality of wordlines, wherein each of the plurality of wordlines corresponds to one of the plurality of rows and is operable during a period to provide a gate bias to select the row corresponding to the wordline such that other rows in the plurality of rows are non-selected rows during the period, wherein each of the plurality of memory cells comprises at least one transistor coupled to receive a back bias;

circuitry for providing a first back bias operable to cause the at least one transistor in each of the memory cells in the selected row to have a first threshold voltage;

circuitry for providing a second back bias operable to cause the at least one transistor in each of the memory cells in at least some of the non-selected rows to have a second threshold voltage during the period;

wherein the first threshold voltage is different than the second threshold voltage; and

wherein the at least one transistor coupled to receive the back bias is coupled to receive the back bias from a buried wordline corresponding to the row.

2. The memory configuration of claim 1 wherein the buried wordline is electrically connected to the wordline corresponding to the row.

3. The memory configuration of claim 1 wherein the buried wordline is electrically disconnected from the wordline corresponding to the row.

4. A memory configuration, comprising:

an array comprising a plurality of memory cells arranged in a plurality of rows and columns;

a plurality of wordlines, wherein each of the plurality of wordlines corresponds to one of the plurality of rows; and

wherein each of the plurality of memory cells comprises at least one transistor coupled to receive a back bias from a wordline corresponding to the row on which the cell is arranged.

5. The memory configuration of claim 4 wherein the at least one transistor comprises an access transistor.

6. The memory configuration of claim 4 wherein the at least one transistor comprises a drive transistor.

7. The memory configuration of claim 4 wherein the at least one transistor comprises a pull-up transistor.

8. The memory configuration of claim 4 wherein the at least one transistor comprises each of an access transistor and a drive transistor.

9. The memory configuration of claim 4 wherein the at least one transistor is coupled to receive the back bias via a direct connection.

10. The memory configuration of claim 4 wherein the at least one transistor is coupled to receive the back bias via a dielectric coupling.

11. A memory configuration, comprising:

a memory array comprising a plurality of memory cells arranged in a plurality of rows and columns;

a plurality of wordlines, wherein each of the plurality or wordlines corresponds to one of the plurality of rows and is operable during a period to provide a gate bias to select the row corresponding to the wordline such that other rows in the plurality of rows are non-selected rows during the period, wherein each of the plurality of memory cells comprises at least one transistor coupled to receive a back bias;

circuitry for providing a first back bias operable to cause the at least one transistor in the each of the memory cells in the selected row to have a first threshold voltage;

circuitry for providing a second back bias operable to cause the at least one transistor in each of the memory cells in at least some on the non-selected rows to have a second threshold voltage during the period;

wherein the first threshold voltage is different than the second threshold voltage; and

wherein the at least one transistor coupled to receive the back bias is coupled to receive the back bias from the wordline corresponding to the row.