Totem pole mixer having grounded serially connected stacked FET pair

• US 6,064,872 A
• Filed: 09/09/1997
• Issued: 05/16/2000
• Est. Priority Date: 03/12/1991
• Status: Expired due to Term

• Current Assignee: WJ Communications, Inc. (Qorvo, Inc.)
• Original Assignee: Watkins Johnson Co. (Qorvo, Inc.)
• Inventors: Vice, Michael Wendell
• Primary Examiner(s): Urban, Edward F.
• Application Number:
  US08/926,175
• Time in Patent Office: 980 Days
• Field of Search: 455/333, 455/318, 455/319, 455/323, 455/332, 327/356, 333/101, 333/24 R, 333/245, 333/246, 333/25, 333/26, 333/117, 333/119, 333/177
• US Class Current: 455/326
• CPC Class Codes: H03D 2200/0023 Balun circuits
• CPC Class Codes: H03D 2200/0088 Reduction of intermodulation, nonlinearities, adjacent channel interference; intercept points of harmonics or intermodulation products
• CPC Class Codes: H03D 7/14 Balanced arrangements
• CPC Class Codes: H03D 7/1433 using bipolar transistors H03D7/145 takes precedence
• CPC Class Codes: H03D 7/1441 using field-effect transistors H03D7/145 takes precedence
• CPC Class Codes: H03D 7/1466 Passive mixer arrangements

Abstract

A high dynamic range mixer apparatus and mixing method where a wide high dynamic range is achieved in part due to the use of a series pair of switching devices that are matched so as to afford complete or substantial cancellation of nonlinearity distortion. The inventive structure and method preserves the compensation and cancellation mechanism of the series pair of back-to-back connected FETs without the need for either of an intermediate frequency (IF) balun or a radio-frequency (RF) balun. Typically, the switching devices are PETs, such as for example MESFETs, connected source-to-source with one drain terminal grounded, and a non-grounded or floating switching signal applied between the common gate and common source terminals.

Claims

1. A signal mixing device for generating a mixer output signal comprising:

a first and a second FET, each having a gate and a drain and a source, said first and second FETs having their gates tied to one another and their sources tied to one another such that said first and second FETs are connected source-to-source in series and have substantially equal magnitude gate-to-source voltages at all times and have substantially equal magnitude but opposite sign drain-to-source voltages at all times, said second FET drain connected to ground;

an RF/IF diplexer circuit connected to said first FET drain and having an RF signal coupling port and an IF signal coupling port for communicating RF and IF signals between said first FET drain and external sources and sinks of RF and IF signals;

a transformer having a primary and secondary portion, said primary portion having a first terminal connected to a LO input port for receiving an external LO input signal and a second terminal connected to ground, said secondary portion having a third terminal connected to said FET gates and a fourth terminal connected to said FET sources, said secondary winding and said FET gates and sources floating and not tied to ground;

said transformer receiving said local oscillator signal and generating a floating drive signal between said joined gate terminals and said joined source terminals to switch the conduction state of said serially connected FETs between a conducting state and a non-conducting state;

said diplexer receiving an input signal and coupling said input signal to said first FET drain, said input signal passing through the channel combination formed by said first and second FETs during the time said FETs are conducting and mixing said floating local oscillator signal with said input signal to generate said output signal;

said first FET introducing a first component of intermodulation distortion in said output signal related to the change in channel resistance of said first FET during channel conduction, and said second FET introducing a second component of intermodulation distortion in said output signal related to the change in channel resistance of said second FET during channel conduction, said second component being about equal in magnitude but opposite in sign to said first component;

said back-to-back serial FET connection being operative to sum and cancel said first distortion component with said second distortion component so that the overall intermodulation distortion introduced in said mixer output signal is suppressed; and

said diplexer having an output port for extracting said output signal.

2. The mixer in claim 1, wherein said input signal is an RF signal and said output signal is an IF signal.

3. The mixer in claim 1, wherein said input signal is an IF signal and said output signal is an RF signal.

4. The mixer in claim 1 wherein each of said diplexer, transformer, and first and second FET are formed on a single integrated monolithic substrate.

5. The mixer in claim 1 further comprising an isolation capacitor, wherein said isolation capacitor is interposed between a terminal of said transformer secondary portion and said FET gate terminals.

6. The mixer in claim 1, wherein said diplexer further comprises:

a first capacitor (C2) having first and second terminals serially connected to a first inductor (L2) having first and second terminals, said second terminal of inductor L2 being grounded and the second terminal of capacitor C2 being connected directly to the Q1 drain;

a second capacitor (C3) having first and second terminals serially connected to a second inductor (L3) having first and second terminals, said second terminal of capacitor C3 being connected to ground and said second terminal of inductor L3 being connected to the drain of Q1 and also to said second terminal of capacitor C2;

said diplexer operating to separate RF and IF frequency signals at an RF port and an IF port.

7. The mixer in claim 6, wherein each of said diplexer, transformer, and first and second FETs are formed on a single integrated monolithic substrate.

8. A mixer circuit comprising:

a first switching device having a first terminal and a second terminal;

a second switching device substantially matched to said first switching device and having a third terminal and a fourth terminal, said first terminal corresponding with said fourth terminal and said second terminal corresponding with said third terminal;

said first and second switching devices being back-to-back serially connected with said second terminal being connected to said third terminal to form a common circuit node and said four terminal being connected directly to ground; and

an isolation circuit adapted to receive an external local oscillator signal at a two-terminal input port and to generate a floating switching signal at a two-terminal output port, said output port coupled to said common circuit node of said first and second switching devices.

9. The mixer circuit in claim 8, wherein said first and second switching devices comprise transistors, said first terminal being a drain and said second terminal being a source of said first transistor, said third terminal being a source and said fourth terminal being a drain of said second transistor, each said transistor further comprising a gate control terminal, said floating switching signal being coupled across said gate control terminal and said common circuit node formed by the connection of said first transistor source and said second transistor source.

10. The mixer circuit in claim 8, wherein said first and second switching devices comprise FETs, each said FET further comprising a common gate terminal wherein said gate terminals are connected together, said first terminal comprising a drain, said second terminal comprising a source, said third terminal comprising a source, and said fourth terminal comprising a drain connected to ground;

said source of said first FET being connected to said source of said second FET, wherein said floating switching signal is coupled across said common gate terminals and said common source terminals.

11. The mixer circuit in claim 8, wherein said isolation circuit comprises a transformer.

12. The mixer circuit in claim 11, wherein said isolation circuit further comprises an isolation capacitor.

13. The mixer in claim 9, further comprising a first impedance element coupled across said first FET drain and source terminals, and a second impedance element coupled across said second FET drain and source terminals.

14. A mixer circuit comprising:

first and second matched FET transistors each having an input terminal, an output terminal, and a control terminal, one of said output terminals being connected directly to ground and the other of said output terminals being connected to the input terminal of said switching device having a grounded output terminal to form a common circuit node;

an isolation circuit adapted to receive an external local oscillator signal at a two-terminal input port and to generate a floating switching signal and couple said floating switching signal across said control terminal and said common circuit node;

a first impedance element coupled across said first FET drain and source terminals comprising a first resistor; and

a second impedance element coupled across said second FET drain and source terminals comprising a second resistor having substantially the same resistance value as said first resistor;

said first and second resistors enforcing voltage synchronization across said first and second FETs and improving third order intercept point of said mixer circuit.

15. A mixer circuit comprising:

first and second matched FET transistors each having an out terminal, an output terminal, and a control terminal, one of said output terminals being connected directly to ground and the other of said output terminals being connected to the input terminal of said switching device having a grounded output terminal to form a common circuit node;

an isolation circuit adapted to receive an external local oscillator signal at a two-terminal input port and to generate a floating switching signal and couple said floating switching signal across said control terminal and said common circuit node;

a first impedance element coupled across said first FET drain and source terminals comprising a first capacitor; and

a second impedance element coupled across said second FET drain and source terminals comprising a second capacitor having substantially the same capacitance value as said first capacitor.

16. A mixer circuit comprising:

first and second matched FET switching elements each having an input terminal and an output terminal, one of said output terminals being connected directly to ground and the other of said output terminals being connected to the input terminal of said switching device having a grounded output terminal to form a common circuit node; and

an isolation circuit having a transformer and an isolation capacitor adapted to receive an external local oscillator signal at a two-terminal input port and to generate a floating switching signal at a two-terminal output port, said output port coupled to said first and second switching devices; and

a compensating switching element including matched third and fourth FETs connected in back-to-back manner at a common source terminal and separately at a common gate terminal, said third and fourth FETs having floating drain terminals;

said first, second, third, and fourth FETs having substantially matched electrical characteristics;

a common gate of said first and second FETs coupled to said common source terminal of said third and fourth FETs, and a common source terminal of said first and second FETs being coupled to said common gate of said third and fourth FETs;

said compensating switching element acting to symmetrize nonlinear capacitance exhibited by said first and second FETs and making them easier to drive by a resonant tuned amplifier and improving the symmetry of the resulting gate drive waveform.

17. A signal mixing device for generating a mixer output signal comprising:

a first FET and a second FET, each said FET having a gate and a drain and a source, said first and second FETs having their gates tied to one another and their sources tied to one another such that said first and second FETs are serially connected source-to-source and have substantially equal magnitude gate-to-source voltages at all times and have substantially equal magnitude but opposite sign drain-to-source voltages at all times, said FET gates and FET sources floating and not tied to ground and said second FET drain connected to ground; and

a drive signal generating circuit generating a floating drive signal between said joined FET gates and said joined FET sources to switch the conduction state of said serially connected FETs between a conducting state and a non-conducting state, said first FET drain receiving an external input signal and said input signal passing through a channel combination formed by said first and second FETs during the time said FETs are conducting and mixing said floating drive signal with said input signal to generate said output signal;

said first FET introducing a first component of intermodulation distortion in said output signal related to the change in channel resistance of said first FET during channel conduction, and said second FET introducing a second component of intermodulation distortion in said output signal related to the change in channel resistance of said second FET during channel conduction, said second component being substantially equal in magnitude but opposite in sign to said first component;

said source-to-source serial FET connection being operative to sum and cancel said first distortion component with said second distortion component so that the overall intermodulation distortion introduced in said mixer output signal is suppressed.

18. The mixer in claim 17, wherein said input signal is an RF signal and said output signal is an IF signal.

19. The mixer in claim 17, wherein said input signal is an IF signal and said output signal is an RF signal.

20. The mixer in claim 17, wherein said drive signal comprises a local oscillator signal.