Duplexer circuit apparatus provided with amplifier and impedance matching inductor

• US 6,066,993 A
• Filed: 07/10/1998
• Issued: 05/23/2000
• Est. Priority Date: 01/16/1998
• Status: Expired due to Fees

• Current Assignee: Mitsubishi Denki Kabushiki Kaisha (Mitsubishi Electric Corporation)
• Original Assignee: Mitsubishi Denki Kabushiki Kaisha (Mitsubishi Electric Corporation)
• Inventors: Yamamoto, Kazuya, Moriwaki, Takao
• Primary Examiner(s): GENSLER, PAUL L
• Application Number:
  US09/113,284
• Time in Patent Office: 683 Days
• Field of Search: 333/103, 333/104, 330/311, 455/78, 455/80, 455/82, 455/83, 327/404
• US Class Current: 333/103
• CPC Class Codes: H03F 1/223 with MOSFET's
• CPC Class Codes: H03F 2200/72 the amplifier stage being a common gate configuration MOSFET
• CPC Class Codes: H03F 2203/7236 the gated amplifier being switched on or off by putting into parallel or not, by choosing between amplifiers by (a ) switch(es)
• CPC Class Codes: H03F 3/193 with field-effect devices H03F3/195 takes precedence
• CPC Class Codes: H03F 3/211 using a combination of several amplifiers H03F3/60 takes precedence
• CPC Class Codes: H03F 3/423 with MOSFET's
• CPC Class Codes: H03F 3/72 Gated amplifiers, i.e. amplifiers which are rendered operative or inoperative by means of a control signal
• CPC Class Codes: H03K 17/693 Switching arrangements with several input- or output-terminals, e.g. multiplexers, distributors logic circuits H03K19/00; code converters H03M5/00, H03M7/00
• CPC Class Codes: H04B 1/48 in circuits for connecting transmitter and receiver to a common transmission path, e.g. by energy of transmitter H04B1/46 takes precedence

Abstract

A duplexer circuit apparatus includes (a) a transmission arm circuit including a first switching circuit which is connected between a transmitter and an antenna, is turned on during transmission, and is turned off during reception, and (b) a reception arm circuit including a second switching circuit which is connected between a receiver and the antenna, is turned off during transmission, and is turned on during reception. In the duplexer circuit apparatus, either the transmitter or the receiver is selectively connected to the antenna, and the transmission arm circuit further includes a cascode amplifier, and an impedance matching inductor connected between the cascode amplifier and the antenna. In this case, the cascode amplifier may be replaced by a source-grounded amplifier constituted by only the FET.

Claims

1. A duplexer circuit apparatus comprising:

a transmission arm circuit connected between a transmitter and an antenna, said transmission arm circuit including a first switching circuit turned on during transmission, and turned off during reception; and

a reception arm circuit connected between a receiver and the antenna, said reception arm circuit including a second switching circuit comprising a plurality of field effect transistors connected in parallel with each other, each of said field effect transistors being turned off during transmission and turned on during reception, whereby either the transmitter or the receiver is selectively connected to the antenna, and wherein said transmission arm circuit comprises;

a cascode amplifier; and

an impedance matching inductor connected between said cascode amplifier and the antenna.

2. A duplexer circuit apparatus comprising:

a transmission arm circuit connected between a transmitter and an antenna, said transmission arm circuit including a first switching circuit turned on during transmission, and turned off during reception; and

a reception arm circuit connected between a receiver and the antenna, said reception arm circuit including a second switching circuit comprising a plurality of field effect transistors connected in parallel with each other, each of said field effect transistors being turned off during transmission and turned on during reception, whereby either the transmitter or the receiver is selectively connected to the antenna, and wherein said transmission arm circuit comprises;

a source-grounded amplifier; and

an impedance matching inductor connected between said source-grounded amplifier and the antenna.

3. A duplexer circuit apparatus comprising:

a transmission arm circuit connected between a transmitter and an antenna, said transmission arm circuit including a first switching circuit turned on during transmission, and turned off during reception; and

a reception arm circuit connected between a receiver and the antenna, said reception arm circuit including a second switching circuit comprising a plurality of field effect transistors connected in parallel and series with each other, each of said field effect transistors being turned off during transmission and turned on during reception whereby either the transmitter or the receiver is selectively connected to the antenna, and wherein said transmission arm circuit comprises;

a cascode amplifier; and

an impedance matching inductor connected between said cascode amplifier and the antenna.

4. A duplexer circuit apparatus for selectively connecting either first or second transmitters or a receiver to an antenna, comprising:

a first transmission arm circuit connected between a first transmitter and an antenna, said first transmission arm circuit including a first switching circuit turned on during transmission, and turned off during reception;

a second transmission arm circuit connected between a second transmitter and the antenna, said second transmission arm circuit including a second switching circuit turned on during transmission, and turned off during reception; and

a reception arm circuit connected between the receiver and the antenna, said reception arm circuit including a third switching circuit turned off during transmission, and turned on during reception, wherein each of said first and second transmission arm circuits comprises;

a cascode amplifier; and

an impedance matching inductor connected between said cascode amplifier and the antenna.

5. The duplexer circuit apparatus as claimed in claim 4, wherein said third switching circuit comprises a plurality of FETs connected in parallel with one another, each of said FETs being turned off during transmission and turned on during reception.

6. The duplexer circuit apparatus as claimed in claim 4, wherein said third switching circuit comprises a plurality of FETs connected in series with one another, each of said FETs being turned off during transmission and turned on during reception.

7. A duplexer circuit device comprising:

a capacitor connected between an antenna and a first node;

an inductor connected between the first node and a second node;

a cascode amplifier for amplifying a signal output from a transmitter, said cascode amplifier including a first transistor connected to the second node and outputting an amplified signal to the second node, said first transistor being turned off during reception; and

a reception arm circuit for transmitting a signal received from the antenna to a receiver, said reception arm circuit including a second transistor connected between the first node and the receiver, said second transistor being turned off during transmission.

8. The duplexer circuit as claimed in claim 7, wherein said cascode amplifier includes a third transistor having a gate connected to the transmitter and a drain connected to said first transistor.

9. A duplexer circuit comprising:

a capacitor connected between an antenna and a first node;

an inductor connected between the first node and a second node;

a source-grounded amplifier for amplifying a signal output from a transmitter, said source-grounded amplifier including a first transistor having a gate connected to the transmitter, a source connected to a ground terminal, and a drain connected to second node, said source-grounded amplifier outputting an amplified signal to the second node, said first transistor being turned off during reception; and

a reception arm circuit for transmitting a signal received from the antenna to a receiver, said reception arm circuit including a second transistor connected between the first node and the receiver, said second transistor being turned off during transmission.

10. A duplexer circuit comprising:

a capacitor connected between an antenna and a first node;

an inductor connected between the first node and a second node;

an amplifier for amplifying a signal output from a transmitter, said amplifier including a first transistor connected to the second node and outputting an amplified signal to the second node, said first transistor being turned off during reception;

a reception arm circuit for transmitting a signal received from the antenna to a receiver, said reception arm circuit including a second transistor connected between the first node and the receiver, said second transistor being turned off during transmission; and

a third transistor connected to said second transistor at a third node, said third transistor being turned off during reception, and a second capacitor connected between said third transistor and a ground terminal.

11. A duplexer circuit comprising:

a capacitor connected between an antenna and a first node;

an inductor connected between the first node and a second node;

an amplifier for amplifying a signal output from a transmitter, said amplifier including a first transistor connected to the second node and outputting an amplified signal to the second node, said first transistor being turned off during reception, and

a reception arm circuit for transmitting a signal received from the antenna to a receiver, said reception arm circuit including a second transistor connected between the first node and the receiver, said second transistor being turned off during transmission, and a third transistor, said third transistor being turned off during reception, said second and third transistors being connected in series between the first node and the receiver.

12. A duplexer circuit comprising:

a capacitor connected between an antenna and a first node;

an inductor connected between the first node and a second node;

an amplifier for amplifying a signal output from a transmitter, said amplifier including a first transistor connected to the second node and outputting an amplified signal to the second node, said first transistor being turned off during reception; and

a reception arm circuit for transmitting a signal received from the antenna to a receiver, said reception arm circuit including a second transistor connected between the first node and the receiver, said second transistor being turned off during transmission, and a third transistor, said third transistor being turned off during reception, said second and third transistors being connected in parallel between the first node and the receiver.

13. A duplexer circuit comprising:

a capacitor connected between an antenna and a first node;

a first inductor connected between the first node and a second node;

a first amplifier for amplifying a signal output from a first transmitter, said first amplifier including a first transistor connected to the second node and outputting an amplified signal to the second node, said first transistor being turned off during reception;

a reception arm circuit for transmitting a signal received from the antenna to a receiver, said reception arm circuit including a second transistor connected between the first node and the receiver, said second transistor being turned off during transmission;

a second inductor connected between the first node and a third node; and

a second amplifier for amplifying a signal output from a second transmitter, said second amplifier including a third transistor connected to the third node and outputting an amplified signal to the third node, said third transistor being turned off during reception.