Method of making embedded flash memory with salicide and sac structure

  • US 6,074,915 A
  • Filed: 08/17/1998
  • Issued: 06/13/2000
  • Est. Priority Date: 08/17/1998
  • Status: Expired due to Term
First Claim
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1. A combined method of forming salicide and SAC structures on a semiconductor device comprising the steps of:

  • providing a semiconductor substrate having well regions;

    defining device regions on said substrate, said device regions comprising a first device region and a second device region;

    forming field oxide regions surrounding and electrically isolating said device regions on said substrate;

    forming a first gate oxide layer on said first and second device regions;

    depositing a first polysilicon layer over said first gate oxide layer and elsewhere on said substrate;

    doping said first polysilicon layer;

    patterning by photoresist masking and anisotropic plasma etching said first polysilicon layer leaving portions over said first device region and exposing said first gate oxide over said second device region;

    forming a first interpoly oxide layer over said portions of said first polysilicon over said first device region and elsewhere on said substrate;

    depositing a second polysilicon layer over said first interpoly oxide layer on said substrate;

    depositing a silicide layer over said second polysilicon layer on said substrate;

    forming a cap layer over said silicide layer on said substrate;

    removing from second device region the stacked layer of cap layer, said silicide layer, said interpoly and intergate oxides and thus exposing surface area of said semiconductor substrate in said second device region;

    forming a second gate oxide layer over said second device region;

    depositing an intrinsic polysilicon layer over said first and second device regions on said substrate;

    patterning by photoresist masking and anisotropic plasma etching said intrinsic polysilicon layer leaving portions over said second device region to form a poly-gate and removing said intrinsic polysilicon from elsewhere on said substrate including said second device regions;

    performing a first ion implant over said second device region;

    forming a stacked gate in said first device region;

    performing a second ion implant over said first device region;

    defining a device source line in said first device region;

    performing a third ion implant in said first device region;

    forming oxide spacers on the side-walls of said stacked gate in said first device region and on the side-walls of said poly-gate in said second device region;

    performing a fourth ion implant to form source and drain regions;

    forming a conformal layer covering said first and second device regions;

    forming a resistor protective oxide layer over said first device region;

    removing said conformal layer from said second device region;

    performing salicidation in said second device region;

    depositing an interlevel dielectric layer over said substrate;

    etching self-aligned contact holes in said interlevel dielectric layer in said first and second device regions; and

    forming metal in said self-aligned contact holes to continue with the completion of the manufacturing of the semiconductor devices.

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