ESD protection circuit for mixed mode integrated circuits with separated power pins

  • US 6,075,686 A
  • Filed: 07/09/1997
  • Issued: 06/13/2000
  • Est. Priority Date: 07/09/1997
  • Status: Expired due to Term
First Claim
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1. An integrated circuit, for protecting first and second internal circuits, respectively connected to either a first or a second power supply bus, against ESD failure, said first and second power supply busses being mutually isolated from each other and being of the same polarity, and said first and second internal circuits being respectively connected to either a third or a fourth power supply bus, said third and fourth power supply busses being mutually isolated from each other, of the same polarity but of opposite polarity as said first and second power supply busses, said integrated circuit comprising:

  • a first I/P block including a first input pad and a first input ESD protection circuit, said first input ESD protection circuit comprising first and second input diodes, said first and second input diodes being connected in series between said first and third power supply busses and being connected in parallel to said first input pad;

    a second I/P block including a second input pad and a second input ESD protection circuit said second input ESD protection circuit comprising third and fourth input diodes, said third and fourth input diodes being connected in series between said second and fourth power supply busses and being connected in parallel to said second input pad;

    a first O/P block including a first output pad and a first output buffer, said first output buffer being connected between said first and third power supply busses and being connected to said first output pad;

    a second O/P block including a second output pad and a second output buffer, said second output buffer being connected between said second and fourth power supply busses and being connected to said second output pad;

    a first interface circuit being connected to said first internal circuit and to said first and third power supply busses;

    a second interface circuit being connected to said second internal circuit, to said second and fourth power supply busses, and to said first interface circuit, such that signals may pass between said first and second internal circuits;

    a first ESD protection circuit connected to said first and third power supply busses,a second ESD protection circuit connected to said second and fourth power supply busses,a third ESD protection circuit connected between said first and second power supply busses for selectively connecting said first and second power supply busses only during an ESD event so that ESD energy applied to one of said first or second power supply busses couples to a second one of said first or second power supply busses, said third ESD protection circuit comprising at least first and second diodes connected in series, said at least first and second diodes being connected in parallel with at least third and fourth diodes connected in series,a fourth ESD protection circuit connected between said third and fourth power supply busses for selectively connecting said third and fourth power supply busses during an ESD event so that ESD energy applied to one of said third or fourth power supply busses couples to a second one of said third or fourth power supply busses, said fourth ESD protection circuit comprising a resistor in parallel with a fifth diode which is in parallel with a sixth diode, andwherein said ESD energy coupled between said first and second power supply busses and between said third and fourth power supply busses is also coupled through at least one of said first or second ESD protection circuits to ground.

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