Gate array semiconductor device

• US 6,084,255 A
• Filed: 07/30/1998
• Issued: 07/04/2000
• Est. Priority Date: 01/29/1998
• Status: Expired due to Fees

• Current Assignee: Renesas Electronics Corporation
• Original Assignee: Mitsubishi Denki Kabushiki Kaisha (Mitsubishi Electric Corporation)
• Inventors: Hirota, Takanori, Mashiko, Koichiro, Wada, Yoshiki, Ueda, Kimio
• Primary Examiner(s): Munson, Gene M.
• Application Number:
  US09/126,092
• Time in Patent Office: 705 Days
• Field of Search: 257/204, 257/206, 257/351
• US Class Current: 257/204
• CPC Class Codes: H01L 27/0207 Geometrical layout of the components, e.g. computer aided design; custom LSI, semi-custom LSI, standard cell technique
• CPC Class Codes: H01L 27/11807 CMOS gate arrays
• CPC Class Codes: H01L 27/1203 the substrate comprising an insulating body on a semiconductor body, e.g. SOI three-dimensional layout H01L27/0688

Abstract

In each of basic cells (BC) arranged in array in an SOI layer, PMOS and NMOS transistors are symmetrically formed. Body regions (11) and (12) are formed to divide source/drain layers (1) and (2), respectively, and gate electrodes (3) and (4) are formed on the body regions (11) and (12) respectively to sandwich gate insulating films therebetween. The gate electrodes (3) and (4) are connected at their both ends to gate contact regions (5) to (8), respectively, and the body regions (11) and (12) are connected at their one ends to body contact regions (9) and (10), respectively. The body contact regions (9) and (10) are so arranged as to sandwich the gate contact regions (5) and (7) together with the gate electrodes (3) and (4), respectively. Being of a SOI type, the device achieves high-speed operation and low power consumption. Further, with positional relation between the body contact regions (9), (10) and the gate contact regions (5), (7), the device is capable of freely setting the transistors to be of either a gate control type or a gate fixed type. As a result, the gate array type semiconductor device achieves high-speed operation and low power consumption.

Claims

1. A semiconductor device of gate array type, comprising:

an insulating layer of electrical insulation; and

a semiconductor layer formed on said insulating layer and defining a major surface on an opposite side of said insulating layer,

said device defining cell regions arranged in a row along said major surface,

said semiconductor layer, in each one of said cell regions, having;

a source/drain region of first conductivity type exposed to said major surface;

a body region of second conductivity type exposed to said major surface and so arranged as to divide said source/drain region into two regions which are placed side by side in a direction of said row; and

a body contact region of second conductivity type exposed to said major surface and linked to an end of said body region,

said device, in each one of said cell regions, further comprising;

a gate insulating film of electrical insulation formed on a portion of said major surface to which said body region is exposed;

a gate electrode of electrical conductance formed on said gate insulating film; and

gate contact regions of electrical conductance formed on said gate insulating film and respectively linked to both ends of said gate electrode,

said body contact region being disposed at such a position that the same and said gate electrode sandwich one of said gate contact regions therebetween,

wherein said semiconductor layer further has;

an isolation insulating film which isolates said body contact region from each other between any adjacent two of said cell regions.

2. The semiconductor device of claim 1, wherein

said device, further defines other cell regions arranged in an another row parallel to said row,

said cell regions and said other cell regions are defined symmetrically with reference to an axis defined between and in parallel to said row and another row,

said semiconductor layer, in each one of said other cell regions, further has:

another source/drain region of second conductivity type exposed to said major surface;

another body region of first conductivity type exposed to said major surface and so arranged as to divide said another source/drain region into two regions which are placed side by side in a direction of said another row; and

another body contact region of first conductivity type exposed to said major surface and linked to an end of said another body region,

said device, in each one of said other cell regions, further comprises;

another gate insulating film of electrical insulation formed on a portion of said major surface to which said another body region is exposed;

another gate electrode of electrical conductance formed on said another gate insulating film; and

an other gate contact regions of electrical conductance formed on said another gate insulating film and respectively linked to both ends of said another gate electrode,

said another body contact region is disposed at such a position that the same and said another gate electrode sandwich one of said other gate contact regions therebetween, and

between any symmetrical two each selected from said cell regions and said other cell regions respectively, said source/drain region and said another source/drain region, said body region and said another body region, said contact region and said another body contact region, said gate insulating film and said another gate insulating film, said gate electrode and said another gate electrode, and, said gate contact regions and said other gate contact regions, are respectively symmetric with reference to said axis.

3. The semiconductor device of claim 2, wherein

said device, in each one of at least a part of said cell regions, further comprises:

a connecting wiring which electrically connects said body contact region and said one of said gate contact regions with each other.

4. The semiconductor device of claim 3, wherein

said device further comprises:

a source wiring for supplying a source potential,

said cell regions include another part thereof excluding said at least a part thereof, and

said device, in each one of said another part of said cell regions, further comprises;

another connecting wiring which electrically connects said body contact region and said source wiring with each other.

5. The semiconductor device of claim 2, wherein

said source/drain region is integrally contiguous with each other between any adjacent two of said cell regions.

6. The semiconductor device of claim 5, wherein

said device further comprises:

a source wiring for supplying a source potential, and

said device, in each one of at least a part of said cell regions, further comprises;

a connecting wiring which electrically connects said source wiring, said body contact region and said one of said gate contact regions with one another.

7. A semiconductor device of gate array type, comprising:

an insulating layer of electrical insulation; and

a semiconductor layer formed on said insulating layer and defining a major surface on an opposite side of said insulating layer,

said device defining cell regions arranged in a row along said major surface,

said semiconductor layer, in each one of said cell regions, having;

a source/drain region of first conductivity type exposed to said major surface;

a body region of second conductivity type exposed to said major surface and so arranged as to divide said source/drain region into two regions which are placed side by side in a direction of said row; and

a body contact region of second conductivity type exposed to said major surface and linked to an end of said body region,

said device, in each one of said cell regions, further comprising;

a gate insulating film of electrical insulation formed on a portion of said major surface to which said body region is exposed;

a gate electrode of electrical conductance formed on said gate insulating film; and

gate contact regions of electrical conductance formed on said gate insulating film and respectively linked to both ends of said gate electrode,

said body contact region being disposed at such a position that the same and said gate electrode sandwich one of said gate contact regions therebetween,

wherein said semiconductor layer, in each one of said cell regions, further has;

another body contact region of second conductivity type exposed to said major surface and linked to another end of said body region, and

said another body contact region is disposed at such a position that the same and said gate electrode sandwich another one of said gate contact regions therebetween.

8. The semiconductor device of claim 7, wherein

said semiconductor layer further has:

an isolation insulating film which isolates said body contact region from each other between any adjacent two of said cell regions; and

another isolation insulating film which isolates said another body contact region from each other between any adjacent two of said cell regions.

9. The semiconductor device of claim 8, wherein

said device, in each one of at least a part of said cell regions, further comprises:

a connecting wiring which electrically connects said body contact region and said one of said gate contact regions with each other; and

another connecting wiring which electrically connects said another body contact region and said another one of said gate contact regions with each other.

10. A semiconductor device of gate array type, comprising:

an insulating layer of electrical insulation; and

a semiconductor layer formed on said insulating layer and defining a major surface on an opposite side of said insulating layer,

said device defining cell regions arranged in a row along said major surface,

said semiconductor layer, in each one of said cell regions, having;

a source/drain region of first conductivity type exposed to said major surface;

a body region of second conductivity type exposed to said major surface and so arranged as to divide said source/drain region into two regions which are placed side by side in a direction of said row; and

a body contact region of second conductivity type exposed to said major surface and linked to an end of said body region,

said device, in each one of said cell regions, further comprising;

a gate insulating film of electrical insulation formed on a portion of said major surface to which said body region is exposed;

a gate electrode of electrical conductance formed on said gate insulating film; and

gate contact regions of electrical conductance formed on said gate insulating film and respectively linked to both ends of said gate electrode,

said body contact region being disposed at such a position that the same and said gate electrode sandwich one of said gate contact regions therebetween,

wherein said device, in each one of at least a part of said cell regions, further comprises;

a connecting wiring lower in electric resistance than said gate electrode, said connecting wiring being disposed over said gate electrode and electrically connecting said gate contact regions with each other which are respectively linked to said both ends of said gate electrode.

11. A semiconductor device of gate array type, comprising:

an insulating layer of electrical insulation; and

a semiconductor layer formed on said insulating layer and defining a major surface on an opposite side of said insulating layer,

said device defining cell regions arranged in a row along said major surface,

said semiconductor layer, in each one of said cell regions, having;

a source/drain region of first conductivity type exposed to said major surface;

a body region of second conductivity type exposed to said major surface and so arranged as to divide said source/drain region into two regions which are placed side by side in a direction of said row; and

a body contact region of second conductivity type exposed to said major surface and linked to an end of said body region,

said device, in each one of said cell regions, further comprising;

a gate insulating film of electrical insulation formed on a portion of said major surface to which said body region is exposed;

a gate electrode of electrical conductance formed on said gate insulating film; and

gate contact regions of electrical conductance formed on said gate insulating film and respectively linked to both ends of said gate electrode,

said body contact region being disposed at such a position that the same and said gate electrode sandwich one of said gate contact regions therebetween,

wherein said body region is narrower in a direction of said row in any portion thereof right under said gate electrode and said gate contact regions than said body contact region.

12. A semiconductor device of gate array type, comprising:

an insulating layer of electrical insulation; and

a semiconductor layer formed on said insulating layer and defining a major surface on an opposite side of said insulating layer,

said semiconductor layer having;

a source/drain region of first conductivity type exposed to said major surface;

a body region of second conductivity type exposed to said major surface and so arranged as to divide said source/drain region into two regions; and

a body contact region of second conductivity type exposed to said major surface and linked to an end of said body region,

said device further comprising;

a gate insulating film of electrical insulation formed on a portion of said major surface to which said body region is exposed;

a gate electrode of electrical conductance formed on said gate insulating film; and

gate contact regions of electrical conductance formed on said gate insulating film and respectively linked to both ends of said gate electrode,

said body contact region being disposed at such a position that the same and said gate electrode sandwich one of said gate contact regions therebetween, and

said body region being narrower in a direction perpendicular to a row formed by said gate electrode, said one of said gate contact regions, and said body contact region in any portion thereof right under said gate electrode and said gate contact regions than said body contact region.