Transistor with local insulator structure

• US 6,084,271 A
• Filed: 11/06/1998
• Issued: 07/04/2000
• Est. Priority Date: 11/06/1998
• Status: Expired due to Fees

• Current Assignee: Advanced Micro Devices, Inc.
• Original Assignee: Advanced Micro Devices, Inc.
• Inventors: Lin, Ming-Ren, Yu, Bin, Pramanick, Shekhar
• Primary Examiner(s): Clark, Sheila V.
• Application Number:
  US09/187,892
• Time in Patent Office: 606 Days
• Field of Search: 257/278, 257/396, 257/288, 257/327, 257/349, 257/647, 257/648, 257/509, 257/510, 257/351, 257/369
• US Class Current: 257/351
• CPC Class Codes: H01L 29/0649 Dielectric regions, e.g. SiO2 regions, air gaps
• CPC Class Codes: H01L 29/6659 with both lightly doped source and drain extensions and source and drain self-aligned to the sides of the gate, e.g. lightly doped drain [LDD] MOSFET, double diffused drain [DDD] MOSFET
• CPC Class Codes: H01L 29/78 with field effect produced by an insulated gate H01L29/7725, H01L29/775, H01L29/778 take precedence
• CPC Class Codes: H01L 29/7833 with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's for thin film transistors H01L29/78618

Abstract

A thin filmed fully-depleted silicon-on-insulator (SOI) metal oxide semiconductor field defect transistor (MOSFET) utilizes a local insulation structure. The local insulative structure includes a buried silicon dioxide region under the channel region. The MOSFET body thickness is very small and yet silicon available outside of the channel region and buried silicon dioxide region is available for sufficient depths of silicide in the source and drain regions. The buried silicon dioxide region can be formed by a trench isolation technique or a LOCOS technique.

Claims

1. An integrated circuit comprising:

a first wafer layer including a plurality of insulator regions disposed in a first semiconductor substrate; and

a second wafer layer above and attached to the first wafer layer, the second wafer layer including a plurality of transistors disposed in a second semiconductor substrate, each of the transistors including a gate disposed between a source region and a drain region, each of the transistors being disposed above a respective insulator region of the insulator regions, wherein a thickness between the insulator region and the gate is less than 80 nm.

2. The integrated circuit of claim 1, wherein the insulator region is formed in a trench isolation process.

3. The integrated circuit of claim 1, wherein the insulator region is formed in a LOCOS process.

4. The integrated circuit of claim 1, wherein the first wafer layer is thicker than the second wafer layer.

5. The integrated circuit of claim 2, wherein the insulator region is formed by etching a trench in the semiconductor substrate and filling the trench with silicon dioxide.

6. The integrated circuit of claim 5, wherein the silicon dioxide is provided in a TEOS process.

7. The integrated circuit of claim 1, wherein a thickness between the respective insulator region and the gate is less than 50 nm.

8. The integrated circuit of claim 1, wherein the first wafer and the second wafer are attached through a hydrogen-based process.

9. An ultra-large scale integrated circuit comprising a plurality of field effect transistors, the transistors including a gate disposed above a channel region, the channel region being between a source region and a drain region, the channel region being located on a first substrate, the channel region being located above a local insulator means for reducing transient enhanced diffusion on a second substrate, the local insulator means is less than 80 nm from the gate, and the first substrate being attached to the second substrate.

10. The integrated circuit of claim 9, wherein the local insulator means is a silicon dioxide region.

11. The integrated circuit of claim 10, wherein the silicon dioxide region is formed in a LOCOS process or a trench isolation process.

12. The integrated circuit of claim 10, wherein the silicon dioxide region is exclusive of the drain region and the source region.

18. The integrated circuit of claim 9, wherein the first wafer has a hydrogenated top surface.

13. A compound semiconductor wafer, comprising:

a first wafer including a plurality of insulation regions disposed in a semiconductor material; and

a second wafer attached above the first wafer, the second wafer including a plurality of gate structures, the gate structures each being disposed between a source and a drain, each of the gate structures being disposed above a respective insulation region of the insulation regions, wherein a distance between a top of the insulation region and a bottom surface of the second wafer is less than 80 nm.

14. The compound semiconductor wafer of claim 13, wherein the insulation regions are less than 80 nm wide.

15. The compound semiconductor wafer of claim 13, wherein the first wafer has a hydrogenated top surface.

16. The compound semiconductor wafer of claim 13, wherein the insulation regions are LOCOS structures.

17. The compound semiconductor wafer of claim 13, wherein the insulation regions are trench insulation structures.

19. The integrated circuit of claim 13, wherein the insulation region is exclusive of the source and drain, whereby the depth of the source and drain are not affected by the insulation region.

20. An ultra-large scale integrated circuit comprising a plurality of field effect transistors, the transistors including a gate disposed above a channel region, the channel region being between a source region and a drain region, the channel region being located on a first substrate, the channel being located above a local insulator means for reducing transient enhanced diffusion on a second substrate, the local insulator means having a thickness of less than 50 nm and the first substrate being attached to the second substrate.