Semiconductor integrated circuit having suppressed leakage currents

• US 6,087,893 A
• Filed: 10/23/1997
• Issued: 07/11/2000
• Est. Priority Date: 10/24/1996
• Status: Expired due to Fees

• Current Assignee: Toshiba Corporation
• Original Assignee: Toshiba Corporation
• Inventors: Fuse, Tsuneaki, Oowaki, Yukihito
• Primary Examiner(s): ZWEIZIG, JEFFERY SHAWN
• Application Number:
  US08/956,956
• Time in Patent Office: 992 Days
• Field of Search: 323/281, 327/77, 327/89, 327/530, 327/534, 327/535, 327/536, 327/537
• US Class Current: 327/537
• CPC Class Codes: G05F 1/46 wherein the variable actually regulated by the final control device is dc G05F1/625 takes precedence

Abstract

A stable high-speed integrated circuit driven by a wide range of low voltages and consuming low power. A MOSFET is used wherein signals are applied to its gate and body for forming a circuit block which comprises a transistor network and at least one buffer circuit. Each buffer circuit has at least two configurations. A plurality of circuit blocks are formed on the same IC chip. Any of the configurations of the buffer circuit may be selected according to the magnitude of the capacitance of the load driven by the circuit block.

Claims

1. A semiconductor integrated circuit having a source power terminal, a ground terminal and an intermediate potential node, said semiconductor integrated circuit comprising:

a main circuit connected between said source power terminal and said intermediate potential node, said main circuit having a MOSFET wherein an input signal for said MOSFET is applied to the gate and body of said MOSFET;

a reference potential generation circuit inserted between said source power terminal and said ground terminal, said reference potential generation circuit generating reference potential in accordance with the leakage current flowing through the junction of the body and the source electrode of said MOSFET; and

a control circuit connected between said intermediate potential node and said ground terminal, said control circuit having said reference potential applied thereto and controlling the voltage of said intermediate potential node in accordance with said reference potential.

2. A semiconductor integrated circuit, as claimed in claim 1, wherein said reference potential generation circuit comprises:

a second MOSFET whose drain electrode, gate and body are connected to said source power terminal; and

a resister connected between the source electrode of said second MOSFET and said ground terminal whereby said reference potential is outputted from the source electrode of said second MOSFET.

3. A semiconductor integrated circuit, as claimed in claim 1, wherein said control circuit comprises:

a second and a third resister serially connected between said intermediate potential node and said ground potential;

a differential operational amplifier having a non-inverting terminal connected to a connection node of said second and third resisters, an inverting terminal to which said reference potential is applied and an output terminal; and

a third MOSFET connected between said intermediate potential node and said ground potential, said third MOSFET having a gate connected to said output terminal of said differential operational amplifier.

4. A semiconductor integrated circuit, as claimed in claim 3, further comprising a booster circuit in which a source power voltage to be supplied to said source power terminal is boosted and the boosted voltage is applied to said differential operational amplifier.

5. A semiconductor integrated circuit, as claimed in claim 1, further comprising:

an analog circuit having a fourth MOSFET operating in the saturation region thereof, and

a booster circuit in which a source power voltage to be supplied to said source power terminal is boosted and the boosted voltage is applied to said analog circuit.

6. A semiconductor integrated circuit, as claimed in claim 3, further comprising:

an analog circuit having a fourth MOSFET operating in the saturation region thereof, and

a booster circuit in which a source power voltage to be supplied to said source power terminal is boosted and the boosted voltage is applied to said differential operational amplifier and said analog circuit.

7. A semiconductor integrated circuit, as claimed in claim 5, further comprising:

a monitor circuit means for maintaining said boosted voltage.

8. A semiconductor integrated circuit, as claimed in claim 6, further comprising:

a monitor circuit means for maintaining said boosted voltage.

9. A semiconductor integrated circuit having a source power terminal, a ground terminal and an intermediate potential node, said semiconductor integrated circuit comprising

a main circuit connected between said source power terminal and said intermediate potential node, said main circuit having a MOSFET wherein an input signal for said MOSFET is applied to the gate and body of said MOSFET;

a reference potential generation circuit inserted between said source power terminal and said ground terminal, said reference potential generation circuit generating reference potential in accordance with the leakage current flowing through the junction of the body and the source electrode of said MOSFET; and

a control circuit connected between said intermediate potential node and said ground terminal, said control circuit controlling the voltage of said intermediate potential node in accordance with said reference potential.