Trenched gate metal oxide semiconductor device and method

• US 6,097,061 A
• Filed: 03/30/1998
• Issued: 08/01/2000
• Est. Priority Date: 03/30/1998
• Status: Expired due to Term

• Current Assignee: Lone Star Silicon Innovations LLC (Tanit Ventures Inc.)
• Original Assignee: Advanced Micro Devices, Inc.
• Inventors: Liu, Yowjuang W., Wollesen, Donald L.
• Primary Examiner(s): Clark, Sheila V.
• Application Number:
  US09/052,051
• Time in Patent Office: 855 Days
• Field of Search: 257/302, 257/330-334, 257/374, 257/388, 257/397, 257/510, 257/520, 257/622, 257/127, 257/153, 257/170, 257/171, 257/175, 257/244, 257/284, 257/332, 257/333
• US Class Current: 257/330
• CPC Class Codes: H01L 29/4933 with a silicide layer contacting the silicon layer, e.g. Polycide gate with a barrier layer between the silicide and silicon layers H01L29/4941
• CPC Class Codes: H01L 29/66621 using etching to form a recess at the gate location etching of semiconductor bodies H01L21/302
• CPC Class Codes: H01L 29/78 with field effect produced by an insulated gate H01L29/7725, H01L29/775, H01L29/778 take precedence

Abstract

A Metal Oxide Semiconductor (MOS) transistor and method for improving device scaling comprises a trenched polysilicon gate formed within a trench etched in a semiconductor substrate and further includes a source region, a drain region, and a channel region. The source and drain region are laterally separated by the trench in which the trenched polysilicon gate is formed and partially extend laterally beneath the bottom surface of the trench. The channel region is formed in the silicon substrate beneath the bottom surface of the trench. In one embodiment, the top surface of the trenched polysilicon gate is substantially planar to the substrate surface. In another embodiment, the top surface and a portion of the trenched polysilicon gate are disposed above the substrate surface.

Claims

1. A semiconductor transistor comprising:

a semiconductor substrate of a first conductivity type;

a source region of a second conductivity type in the semiconductor substrate;

a drain region of the second conductivity type spaced from the source region in the semiconductor substrate;

a trench having substantially upright vertical surfaces and a bottom surface formed in the semiconductor substrate intermediate the source and drain regions;

a channel region formed in the semiconductor substrate, the channel region forming a contiguous region beneath the bottom surface of the trench and immediately contiguous to the source and drain regions;

a trench-to-gate insulating layer formed on the substantially upright vertical surfaces and the bottom surface inside the trench, the trench-to-gate insulating layer forming a contiguous layer inside the trench; and

a trenched gate electrode having a top surface and formed on the trench-to-gate insulating layer inside the trench.

2. The semiconductor transistor of claim 1 wherein the first conductivity type is n-type and the second conductivity type is p-type.

3. The semiconductor transistor of claim 1 wherein the first conductivity type is p-type and the second conductivity type is n-type.

4. The semiconductor transistor of claim 1 wherein the trench-to-gate insulating layer further comprises:

a trench spacer dielectric layer formed on the substantially upright vertical surfaces inside the trench; and

a trench dielectric formed on the bottom surface inside the trench.

5. The semiconductor transistor of claim 1 wherein the top surface of the trenched gate electrode is substantially planar to the substrate surface.

6. The semiconductor transistor of claim 5 further comprising a layer of tungsten silicide formed on the top surface of the trenched gate electrode.

7. The semiconductor transistor of claim 1 wherein the source and drain regions are formed by a self-limited diffusion process.

8. The semiconductor transistor of claim 1 wherein the top surface and a portion of the trenched gate electrode are disposed above the top surface of the semiconductor substrate.

9. The semiconductor transistor of claim 8 further comprising a layer of tungsten silicide formed on the top surface.

10. The semiconductor transistor of claim 9 further comprising a layer of tungsten silicide formed on the substantially upright vertical side surfaces of the trenched gate electrode.

11. A semiconductor device comprising an array of multiple device structures supported on a semiconductor substrate of a first conductivity type, each device structure spaced from other device structures and comprising:

a source diffusion region of a second conductivity type in the semiconductor substrate;

a drain diffusion region of the second conductivity type spaced from the source diffusion region in the semiconductor substrate;

a trench having substantially upright vertical surfaces and a bottom surface formed in the semiconductor substrate intermediate the source and drain diffusion regions;

a channel region formed in the semiconductor substrate, the channel region forming a contiguous region beneath the bottom surface of the trench and immediately contiguous the source and drain diffusion regions;

a trench-to-gate insulating layer formed on the substantially upright vertical surfaces and the bottom surface inside the trench, the trench-to-gate insulating layer forming a contiguous layer inside the trench; and

a trenched gate electrode formed on the trench-to-gate insulating layer inside the trench.

12. The semiconductor device of claim 11 wherein the first conductivity type is n-type and the second conductivity type is p-type.

13. The semiconductor device of claim 11 wherein the first conductivity type is p-type and the second conductivity type is n-type.

14. The semiconductor device of claim 11 wherein the trench-to-gate insulating layer further comprises:

a trench spacer dielectric layer formed on the substantially upright vertical surfaces inside the trench; and

a trench dielectric formed on the bottom surface inside the trench.

15. The semiconductor device of claim 11 wherein a top surface of the trenched gate electrode is substantially planar to the top surface of the semiconductor substrate.

16. The semiconductor device of claim 15 further comprising a layer of tungsten silicide formed on the top surface of the trenched gate electrode.

17. The semiconductor device of claim 11 wherein a top surface and a portion of the trenched gate electrode are disposed above the top surface of the semiconductor substrate.