Sensing circuit and method

• US 6,101,145 A
• Filed: 12/21/1998
• Issued: 08/08/2000
• Est. Priority Date: 12/21/1998
• Status: Expired due to Term

• Current Assignee: North Star Innovations Inc. (Wi-LAN Inc.)
• Original Assignee: Motorola, Inc. (Motorola Solutions, Inc.)
• Inventors: Nicholes, James W.
• Primary Examiner(s): Fears, Terrell W.
• Application Number:
  US09/216,703
• Time in Patent Office: 596 Days
• Field of Search: 365/189.01, 365/189.05, 365/230.01, 365/230.06, 365/233, 365/210
• US Class Current: 365/230.01
• CPC Class Codes: G11C 7/065 Differential amplifiers of latching type
• CPC Class Codes: G11C 7/067 Single-ended amplifiers

Abstract

The occurrence of invalid data transitions on an output data bus (17) are reduced with an improved data sensing circuit (20). In a single block memory application, a self-controlled sense amplifier (21) eliminates the need for external timing control signals by triggering off the rail-to-rail voltage swings of a complementary bit line pair (BIT, BITB) of a memory array coupled to the inputs of the amplifier (21). Triggering off the bit lines (BIT, BITB) ensures that the amplifier (21) is not activated until valid data appears at its input, thereby preventing glitches on the output data bus (17) due to the amplifier (21) or associated latch (13). In a multiblock memory application, the data sensing circuit is further improved by eliminating invalid data transitions from appearing on the output data bus (17) through use of feedback. Data storage devices (13) of inactive blocks are preloaded with the valid data appearing on the output data bus (17) via a feedback circuit (23), thereby preventing potentially invalid data otherwise stored in an in active storage device (13) from being transferred to the output data bus upon activation.

Claims

1. A sensing circuit for sensing data from a memory array and providing the sensed data to an output data bus, the circuit comprising:

a sense amplifier coupled to the memory array;

a data storage device coupled between the sense amplifier and the output data bus; and

a data feedback circuit having an input terminal coupled to the output data bus and an output terminal coupled to the data storage device.

2. The circuit of claim 1 wherein the sense amplifier comprises a logic sense amplifier having a first input terminal for coupling to a first bit line of a complementary bit line pair and a second input terminal for coupling to a second bit line of the complementary bit line pair, wherein the logic sense amplifier is triggered off signals appearing coupled to the first input terminal and the second input terminal.

3. The circuit of claim 1 wherein the sense amplifier comprises:

a first transistor of a first conductivity type having a current carrying electrode coupled to the data storage device and a control electrode for coupling to a bit line of a complementary bit line pair of the memory array;

a first inverter having an input terminal for coupling to a complementary bit line of the complementary bit line pair; and

a second transistor of a second conductivity type having a current carrying electrode coupled to the current carrying electrode of the first transistor and a control electrode coupled to an output terminal of the first inverter.

4. The circuit of claim 3 wherein the sense amplifier further comprises:

a third transistor of the first conductivity type having a current carrying electrode coupled to the data storage device and a control electrode coupled to the input terminal of the first inverter;

a second inverter having an input terminal for coupling to the bit line of the complementary bit line pair;

a fourth transistor of the second conductivity type having a current carrying electrode coupled to the current carrying electrode of the third transistor and a control electrode coupled to an output terminal of the second inverter.

5. The circuit of claim 1 wherein the data storage device comprises:

a first inverter having an input terminal coupled to the sense amplifier and an output terminal; and

a second inverter having an input terminal coupled to the output terminal of the first inverter and an output terminal coupled to the input terminal of the first inverter.

6. The circuit of claim 1 further comprising an output buffer having an input terminal coupled to the data storage device and an output terminal coupled to the output data bus.

7. The circuit of claim 6 further comprising an inverter coupled between the data storage device and the input terminal of the output buffer.

8. The circuit of claim 1 wherein the data feedback circuit comprises:

a first NOR gate having an input coupled to the output data bus;

a second NOR gate having an input coupled to an output of the first NOR gate;

an inverter having an input coupled to the output of the first NOR gate;

a first transistor of a first conductivity type having a control electrode coupled to an output of the inverter and a current carrying electrode coupled to the output terminal of the data feedback circuit; and

a second transistor of a second conductivity type having a control electrode coupled to an output of the second NOR gate and a current carrying electrode coupled to the output terminal of the data feedback circuit.

9. The circuit of claim 1 wherein the data feedback circuit comprises:

a first NOR gate having an input terminal coupled to the output data bus;

a second NOR gate having an input terminal coupled to an output terminal of the first NOR gate;

a NAND gate having a first input terminal coupled to the output terminal of the first NOR gate and a second input terminal coupled for receiving an enable signal;

a first transistor of a first conductivity type having a control electrode coupled to an output terminal of the NAND gate and a current carrying electrode coupled to the output terminal of the data feedback circuit;

a second transistor of a second conductivity type having a control electrode coupled to an output of the second NOR gate and a first current carrying electrode coupled to the output terminal of the data feedback circuit, and

a third transistor of the second conductivity type having a control electrode coupled for receiving the enable signal and a current carrying electrode coupled to a second current carrying electrode of the second transistor.

10. A self-controlled sense amplifier for sensing data from a memory array, the amplifier comprising:

a first input terminal for coupling to a first bit line of a complementary bit line pair of the memory array;

a second input terminal for coupling to a second bit line of the complementary bit line pair; and

means for sensing data appearing at the first input terminal and the second input terminal, the means coupled between the first and second input terminals and an output terminal of the self-controlled sense amplifier.

11. The amplifier of claim 10 wherein the means for sensing comprises:

a first transistor of a first conductivity type having a current carrying electrode coupled to a first output terminal of the amplifier and a control electrode coupled to the first input terminal;

a first inverter having an input terminal coupled to the second input terminal; and

a second transistor of a second conductivity type having a current carrying electrode coupled to the current carrying electrode of the first transistor and a control electrode coupled to an output terminal of the first inverter.

12. The amplifier of claim 11 wherein the means for sensing further comprises:

a third transistor of a first conductivity type having a current carrying electrode coupled to a second output terminal of the amplifer and a control electrode coupled to the second input terminal;

a second inverter having an input terminal coupled to the first input terminal; and

a fourth transistor of the second conductivity type having a current carrying electrode coupled to the current carrying electrode of the third transistor and a control electrode coupled to an output terminal of the second inverter.

13. The amplifier of claim 12 wherein the first input terminal is coupled to the first bit line of the complementary bit line pair and the second input terminal is coupled to the second bit line of the complementary bit line pair.

14. The amplifier of claim 13 wherein the self-controlled sense amplifier comprises a logic sense amplifier responsive to logic signals received at the first input terminal and the second input terminal, wherein the logic signals transition between a positive most supply voltage and a negative most supply voltage.

15. A method for controlling data transitions on an output data bus of a semiconductor device having a memory array comprising the steps of:

sensing data appearing on a bit line of the memory array;

driving the sensed data onto the output data bus; and

providing a feedback signal representative of the sensed data appearing on the output data bus to inactive memory blocks of the memory array coupled to the output data bus.

16. The method of claim 15 further comprising the step of disabling the feedback signal to an active memory block of the memory array.

17. The method of claim 15 further comprising the step in response to the feedback signal, storing the sensed data in the inactive memory blocks of the memory array.

18. The method of claim 17 wherein the step of sensing data comprises the steps of:

activating a sensing means with a signal transitioning from a first logic level to a second logic level provided at an data input of the sensing means;

sensing with the sensing means data appearing on the bit line of the memory array; and

latching the sensed data in a data storage means.

19. The method of claim 18 the step of driving the sensed data onto the output data bus comprises the step of:

driving the sensed data latched in the data storage means into an output buffer; and

wherein the output buffer drives the sensed data onto the output data bus.