Active pixel sensor with intra-pixel charge transfer

• US 6,101,232 A
• Filed: 11/16/1995
• Issued: 08/08/2000
• Est. Priority Date: 01/28/1994
• Status: Expired due to Term

• Current Assignee: California Institute of Technology
• Original Assignee: California Institute of Technology
• Inventors: Fossum, Eric R., Kemeny, Sabrina E., Mendis, Sunetra
• Primary Examiner(s): Munson, Gene M.
• Application Number:
  US08/558,521
• Time in Patent Office: 1,727 Days
• Field of Search: 257/239, 257/292, 257/294, 377/60, 327/91, 327/94, 327/188, 327/32
• US Class Current: 377/60
• CPC Class Codes: G11C 19/282 with charge storage in a depletion layer, i.e. charge coupled devices [CCD]
• CPC Class Codes: G11C 19/285 Peripheral circuits, e.g. for writing into the first stage; for reading-out of the last stage
• CPC Class Codes: H01L 27/14601 Structural or functional details thereof
• CPC Class Codes: H01L 27/14603 Special geometry or disposition of pixel-elements, address-lines or gate-electrodes
• CPC Class Codes: H01L 27/14621 Colour filter arrangements
• CPC Class Codes: H01L 27/14627 Microlenses
• CPC Class Codes: H01L 27/14645 Colour imagers
• CPC Class Codes: H01L 27/14656 Overflow drain structures
• CPC Class Codes: H01L 27/14843 Interline transfer
• CPC Class Codes: H01L 27/1485 Frame transfer
• CPC Class Codes: H01L 27/14887 Blooming suppression
• CPC Class Codes: H01L 31/02162 for filtering or shielding light, e.g. multicolour filters for photodetectors
• CPC Class Codes: H01L 31/0232 Optical elements or arrangements associated with the device H01L31/0236 takes precedence; for photovoltaic cells H01L31/054; for photovoltaic modules H02S40/20
• CPC Class Codes: H04N 23/10 for generating image signals from different wavelengths
• CPC Class Codes: H04N 25/616 involving a correlated sampling function, e.g. correlated double sampling [CDS] or triple sampling
• CPC Class Codes: H04N 25/63 applied to dark current
• CPC Class Codes: H04N 25/65 applied to reset noise, e.g. KTC noise related to CMOS structures by techniques other than CDS
• CPC Class Codes: H04N 25/677 for reducing the column or line fixed pattern noise
• CPC Class Codes: H04N 25/70 SSIS architectures; Circuits associated therewith
• CPC Class Codes: H04N 25/75 Circuitry for providing, modifying or processing image signals from the pixel array
• CPC Class Codes: H04N 25/76 : Addressed sensors, e.g. MOS or CMOS sensors
• CPC Class Codes: H04N 25/77 : Pixel circuitry, e.g. memories, A/D converters, pixel amplifiers, shared circuits or shared components
• CPC Class Codes: H04N 25/771 : comprising storage means other than floating diffusion

Abstract

An imaging device formed as a monolithic complementary metal oxide semiconductor integrated circuit in an industry standard complementary metal oxide semiconductor process, the integrated circuit including a focal plane array of pixel cells, each one of the cells including a photogate overlying the substrate for accumulating photo-generated charge in an underlying portion of the substrate, a readout circuit including at least an output field effect transistor formed in the substrate, and a charge coupled device section formed on the substrate adjacent the photogate having a sensing node connected to the output transistor and at least one charge coupled device stage for transferring charge from the underlying portion of the substrate to the sensing node.

Claims

1. An imaging device including a monolithic semiconductor integrated circuit substrate, said imaging device comprising a focal plane array of pixel cells, each one of said cells comprising:

a photogate overlying said substrate, accumulating photo-generated charge in an underlying portion of said substrate;

a readout circuit comprising at least an output transistor formed in said substrate;

a coupling section, formed on said substrate adjacent said photogate, having a sensing node connected to said output transistor and at least one coupling stage which transfers charge from said underlying portion of said substrate to said sensing node; and

wherein said readout circuit is a complementary metal oxide semiconductor (CMOS) circuit formed on said substrate, said substrate being of a first conductivity type, said CMOS circuit comprising plural metal oxide field effect transistors of a first conductivity type, a well region of a second conductivity type in said substrate and plural metal oxide semiconductor transistors of a second conductivity type formed in said well region.

2. The imaging device of claim 1 wherein:

said sensing node of said coupling section comprises a floating node; and

said charge coupled device stage comprises a transfer gate between said floating node and said photogate.

3. The imaging device of claim 2 wherein said floating node is one of:

(a) a floating diffusion, and (b) a floating gate.

4. The imaging device of claim 2 further comprising:

a drain diffusion connected to a drain bias voltage; and

a reset gate between said floating node and said drain diffusion, said reset gate connected to a reset control signal.

5. The imaging device of claim 4 wherein said output transistor comprises a field effect source follower transistor, said floating node being connected to a gate of said source follower transistor.

6. The imaging device of claim 4 wherein said readout circuit further comprises a double correlated sampling circuit comprising:

a pair of sample and hold field effect transistors formed in said substrates, each sample and hold field effect transistor having one of a source and drain thereof connected to a source of said source follower transistor;

a pair of sample and hold capacitors connected to the other one of the source and drain of a respective one of said pair of sample and hold transistors; and

means for sensing a potential of each of said sample and hold capacitors at respective intervals.

7. The imaging device of claim 6 further comprising means for sensing a difference between the potentials of said pair of sample and hold capacitors. measures a fixed pattern noise difference.

8. The imaging device of claim 1 further comprising means for periodically resetting a potential of said sensing node to a predetermined potential.

9. The imaging device of claim 1 wherein said readout circuit further comprises a double correlated sampling circuit having an input node connected to said output transistor.

10. The imaging device of claim 1 further comprising a micro-lens layer overlying said substrate, said micro-lens layer comprising:

a refractive layer;

individual lenses formed in said layer in regisration with individual ones of said cells, each of said individual lenses having a curvature for focusing light toward a center portion of the respective cell.

11. The imaging device of claim 10 wherein said refractive layer comprises a polymer.

12. The imaging device of claim 11 wherein said refractive layer comprises polyimide.

13. The imaging device of claim 10 wherein each of said individual lenses covers portions of the corresponding cell including said photogate as well as said charge coupled device stage and said readout circuit.

14. The device of claim 1 wherein said CMOS circuit comprises a double correlated sampling circuit.

15. A device as in claim 1, wherein said readout circuit further includes a correlated double sampling circuit operating to first read a reset value from said sensing node, and next read a sample value from said sensing node, and to output a signal indicative of a difference between said reset value and said sample value.

16. An imaging device including a monolithic semiconductor integrated circuit substrate, said imaging device comprising a focal plane array of pixel cells, each one of said cells comprising:

a photogate overlying said substrate, accumulating photo-generated charge in an underlying portion of said substrate;

a readout circuit comprising at least an output transistor formed in said substrate;

a coupling section formed on said substrate adjacent said photogate, having a sensing node connected to said output transistor and at least one coupling stage, transferring charge from said underlying portion of said substrate to said sensing node;

wherein said sensing node of said coupling stage comprises a floating node and said coupling stare comprises a transfer gate between said floating node and said photogate;

a drain diffusion connected to a drain bias voltage;

a reset gate between said floating node and said drain diffusion, said reset gate connected to a reset control signal;

wherein said readout circuit further comprises a double correlated sampling circuit comprising;

a pair of sample and hold field effect transistors formed in said substrate, each sample and hold field effect transistor having one of a source and drain thereof connected to a source of said output transistor;

a pair of sample and hold capacitors connected to the other one of the source and drain of a respective one of said pair of sample and hold transistors;

means for sensing a potential of each of said sample and hold capacitors at respective intervals; and

means for shorting across each of said pair of sample and hold capacitors simultaneously while said means for sensing measures a fixed pattern noise difference.

17. An imaging device including a monolithic semiconductor integrated circuit substrate, said imaging device comprising a focal plane array of pixel cells, each one of said cells comprising:

a photogate overlying said substrate, accumulating photo-generated charge in an underlying portion of said substrate;

a readout circuit comprising at least an output transistor formed in said substrate;

a coupling section formed on said substrate adjacent said photogate, having a sensing node connected to said output transistor and at least one coupling stage for transferring charge from said underlying portion of said substrate to said sensing node;

wherein said sensing node of said coupling stage comprises a floating node and said coupling stare comprises a transfer gate between said flowing node and said photogate;

a drain diffusion connected to a drain bias voltage;

a reset gate between said floating node and said drain diffusion, said reset gate connected to a reset control signal;

wherein said readout circuit further comprises a double correlated sampling circuit comprising;

a pair of sample and hold field effect transistors formed in said substrate, each sample and hold field effect transistor having one of a source and drain thereof connected to a source of said output transistor;

a pair of sample and hold capacitors connected to the other one of the source and drain of a respective one of said pair of sample and hold transistors;

means for sensing a potential of each of said sample and hold capacitors at respective intervals;

wherein said focal plane array of cells is organized by rows and columns of said cells, and wherein said means for sensing comprises;

a row select field effect transistor formed in said substrate having its source and drain connected between said source of said source follower transistor and said pair of sample and hold transistors and a gate connected to a row select signal;

a pair of sample and hold output transistors having respective gates and sources connected across respective ones of said pair of sample and hold capacitors, and having respective drains;

respective differential output nodes of said correlated double sampling circuit; and

a pair of column select transistors formed in said substrate, each having a source and drain connected between a drain of a respective one of said sample and hold output transistors and a gate connected to a column select signal.

18. The imaging device of claim 17 wherein each of said transistors is a metal oxide field effect transistor, said source follower transistor, said row select transistor and said pair sample and hold transistors being n-channel devices, said pair of sample and hold output transistors and said pair of column select transistors being p-channel devices.

19. An imaging device comprising:

a semiconductor substrate;

a plurality of L-shaped photogates, each overlying a porting of said substrate and each defining a pixel, each operating to accumulate photo-generated charge in the portion of said substrate that underlines said photogate;

a plurality of charge transfer sections and readout circuits formed outside and adjoining said L-shaped photogate so that any photogate and is associated charge transfer section and readout circuits collectively define a rectangular area on said substrate, wherein said readout circuit includes a correlated double sampling element which stores the charge received from said substrate, and a shorting element which shorts across the sampling element after the charge is read, and wherein said readout circuit includes a first charge storage element operating to receive a charge prior to charge transfer, a second charge storage element operating to receive a charge subsequent to charge transfer, and said shorting element comprises a device which shorts together said first and second charge storage elements.

20. An imaging device, comprising:

a substrate of a type which can store optical charge therein, said substrate formed of a plurality of pixel cells, each pixel cell comprising;

an optical charge storage section, including a photogate overlying a portion of said substate;

a charge transfer section, having a floating sensing node, and having a first state in which charge in the portion of the substrate is isolated from the sensing node and a second state in which charge in the substrate is coupled to said sensing node; and

a readout circuit, having an input connected to said floating sensing node, said readout circuit connected to no other nodes of any of the other pixel cells of the device so that each optical charge storage section and charge transfer section is associated with only one readout circuit,

wherein said floating sensing node of said charge transfer section includes a first floating element, which is initially isolated from charge stored in the substrate and is later coupled to the charge stored in the substrate, and

wherein said readout circuit includes a first sampling element for sampling an initial potential on the first floating element while said charge transfer section is isolated from said first floating element, and a second sampling element for sampling a later potential on said floating element when said charge transfer section is coupled to the first floating element, and wherein said readout circuit includes circuitry subtracting said initial potential from said later potential to produce a difference, and wherein an output of said readout circuit is proportional to the difference; and

a shorting element, operating after said difference is determined to connect the potential on said first sampling element to the potential on said second sampling element.

21. A device as in claim 20, wherein said shorting element is a field effect transistor.

22. An imaging device, comprising:

a substrate of a type which can store optical charge therein, said substrate formed of a plurality of pixel cells, each pixel cell comprising;

a) an optical charge storage section, including a photogate overlying a portion of said substrate; and

b) a charge transfer section, having a sensing node, and having a first state in which charge in the portion of the substrate is isolated from the sensing node and a second state in which charge in the substrate is coupled to said sensing node;

a plurality of readout circuits, each said readout circuit having an input connected to said sensing node of a corresponding charge transfer section, each said readout circuit including a first sampling element for sampling an initial potential on the first floating element while said charge transfer section is isolated from said first floating element, and a second sampling element for sampling a later potential on said floating element when said charge transfer section is coupled to the first floating element, and a shorting element, to connect the potential on said first sampling element to the potential on said second sampling element between samplings; and

wherein each said pixel cell comprises a light refracting layer formed over the photogate to refract light that would otherwise have been incident on an area of the substrate that includes at least said readout circuits to the optical charge storage section.

23. An imaging device as in claim 22, wherein each said readout circuit is connected to no other nodes of any of the other pixel cells of the device so that each optical charge storage section and charge transfer section is associated with only one readout circuit.