Method for forming high breakdown semiconductor device

• US 6,103,578 A
• Filed: 04/02/1999
• Issued: 08/15/2000
• Est. Priority Date: 02/10/1997
• Status: Expired due to Fees

• Current Assignee: Mitsubishi Denki Kabushiki Kaisha (Mitsubishi Electric Corporation)
• Original Assignee: Mitsubishi Denki Kabushiki Kaisha (Mitsubishi Electric Corporation)
• Inventors: Minato, Tadaharu, Uenishi, Akio
• Primary Examiner(s): Niebling, John F.
• Assistant Examiner(s): Simkovic, Viktor
• Application Number:
  US09/283,751
• Time in Patent Office: 501 Days
• Field of Search: 438/184, 438/303, 438/338, 438/366, 438/639, 438/268, 438/270, 438/299, 438/302, 438/305
• US Class Current: 438/268
• CPC Class Codes: H01L 21/2252 using predeposition of impurities into the semiconductor surface, e.g. from a gaseous phase
• CPC Class Codes: H01L 21/2255 the applied layer comprising oxides only, e.g. P2O5, PSG, H3BO3, doped oxides
• CPC Class Codes: H01L 21/26513 of electrically active species
• CPC Class Codes: H01L 21/26546 of electrically active species
• CPC Class Codes: H01L 21/26586 characterised by the angle between the ion beam and the crystal planes or the main crystal surface
• CPC Class Codes: H01L 29/0619 with a supplementary region doped oppositely to or in rectifying contact with the semiconductor containing or contacting region, e.g. guard rings with PN or Schottky junction
• CPC Class Codes: H01L 29/0634 Multiple reduced surface field (multi-RESURF) structures, e.g. double RESURF, charge compensation, cool, superjunction (SJ), 3D-RESURF, composite buffer (CB) structures
• CPC Class Codes: H01L 29/0653 adjoining the input or output region of a field-effect device, e.g. the source or drain region
• CPC Class Codes: H01L 29/408 with an insulating layer with a particular dielectric or electrostatic property, e.g. with static charges or for controlling trapped charges or moving ions, or with a plate acting on the insulator potential or the insulator charges, e.g. for controlling charges effect or potential distribution in the insulating layer, or with a semi-insulating layer contacting directly the semiconductor surface
• CPC Class Codes: H01L 29/66712 Vertical DMOS transistors, i.e. VDMOS transistors
• CPC Class Codes: H01L 29/7802 Vertical DMOS transistors, i.e. VDMOS transistors
• CPC Class Codes: H01L 29/7811 with an edge termination structure guard regions per se H01L29/0619; field plates per se H01L29/402
• CPC Class Codes: H01L 29/7813 with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236
• CPC Class Codes: H01L 29/7824 with a substrate comprising an insulating layer, e.g. SOI-LDMOS transistors

Abstract

An n type diffusion region and a p type diffusion region are formed in a region sandwiched between trenches arranged at a first main surface of a semiconductor substrate. A p type well is formed in the n- and p-type diffusion regions nearer the first main surface. A source n⁺ diffusion region is formed at the first main surface within the p type well. A gate electrode layer is formed opposite to the p type well sandwiched between the n type diffusion region and the source n⁺ diffusion region with a gate insulating layer disposed therebetween. The n- and p-type diffusion regions each have an impurity concentration distribution diffused from a sidewall surface of a trench. Thus, a fine, micron-order pn repeat structure can be achieved with sufficient precision and a high breakdown voltage semiconductor device is thus obtained which has superior on-state voltage and breakdown voltage as well as fast switching characteristics.

Claims

1. A high breakdown voltage semiconductor device comprising:

a semiconductor substrate having first and second main surfaces opposite to each other and having a plurality of gaps provided at said first main surface;

a first impurity region of a first conductivity type formed within a region of said semiconductor substrate sandwiched between one and another gaps of said plurality of gaps;

a second impurity region of a second conductivity type formed in said first impurity region nearer said first main surface;

a third impurity region of the first conductivity type formed at said first main surface, opposite to said first impurity region with said second impurity region disposed therebetween; and

a gate electrode layer disposed opposite to said second impurity region sandwiched between said first and third impurity regions with a gate insulating layer disposed between said second impurity region and said gate electrode layer;

wherein

said gap is filled with a filling insulating layer having a fixed charge of an opposite polarity substantially equal in amount to charge within said first impurity region when said first impurity region is depleted.

2. A method of manufacturing a high breakdown voltage semiconductor device, comprising the steps of:

forming a first impurity region of a first conductivity type at a semiconductor substrate having first and second main surfaces opposite to each other nearer said first main surface;

forming at said first main surface a first plurality of gaps deeper than said first impurity region;

forming at said first main surface a second plurality of gaps deeper than said first impurity region;

introducing an impurity of the first conductivity type at one sidewall surface of said first gap by a method having impurity concentration controllability of high precision not affecting a final performance of the semiconductor device to form a second impurity region of the first conductivity type;

introducing an impurity of the second conductivity type at one sidewall surface of said second gap by a method having impurity concentration controllability of high precision not affecting the final performance of the semiconductor device to form a third impurity region of the second conductivity type; and

with a filling layer of one of insulating film and semi-insulating film filling said first and second gaps, diffusing said impurities of the first and second conductivity types introduced at said one sidewall surface of said first and second gaps to form said second impurity region on said one sidewall surface of said first gap and said third impurity region on said one sidewall surface of said second gap in contact with each other in said first impurity region nearer said second main surface.

3. The method of manufacturing a high breakdown voltage semiconductor device according to claim 2, wherein:

said first plurality of gaps and said second plurality of gaps are formed in a same step so that said first gap and said second gap are alternately arranged;

said first and second plurality of gaps have said one sidewall surface and the other sidewall surface disposed opposite thereto;

said impurity of the first conductivity type is introduced at said one sidewall surface of said first gap and at said other sidewall surface of said second gap; and

said impurity of the second conductivity type is introduced at said other sidewall surface of said first gap and at said one sidewall surface of said second gap.

4. The method of manufacturing a high breakdown voltage semiconductor device according to claim 2, wherein;

said impurity of the first conductivity type is introduced at both sidewall surfaces of said first gap

said second plurality of gaps are formed after said impurity of the first conductivity type is introduced such that said second plurality of gaps and said first plurality of gaps are alternately arranged; and

said impurity of the second conductivity type is introduced at both sidewall surfaces of said second gap.

5. The method of manufacturing a high breakdown voltage semiconductor device according to claim 3, wherein said method having impurity concentration controllability of high precision not affecting the final performance of said semiconductor device is oblique iron implantation method.

6. The method of manufacturing a high breakdown voltage semiconductor device according to claim 4, wherein said method having impurity concentration controllability of high precision not affecting the final performance of said semiconductor device is oblique, rotational iron implantation method.