Methods and arrangements for improved spacer formation within a semiconductor device

CAFC
  • US 6,103,611 A
  • Filed: 12/18/1997
  • Issued: 08/15/2000
  • Est. Priority Date: 12/18/1997
  • Status: Expired due to Term
First Claim
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1. A method for forming substantially uniformly sized spacers on transistor gate arrangements within semiconductor devices on a common substrate, the method comprising:

  • forming a plurality of gate arrangements on a top surface of the substrate, wherein two of the plurality of gate arrangements are positioned parallel to one another and separated by a defined space;

    forming a dielectric layer over at least a portion of the two gate arrangements and at least a portion of the defined space;

    removing portions of the dielectric layer to form a plurality of spacers, wherein each of the plurality of spacers physically contacts one of the two gate arrangements and the substrate, and wherein the spacers located within the defined space each have a base width that is approximately the same;

    configuring one of the two gate arrangements to control an electrical current between a source region and a drain region formed in the substrate; and

    configuring the remaining one of the two transistor gate arrangements to be non-operational.

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