Memory cell with vertical transistor and buried word and body lines

• US 6,104,061 A
• Filed: 02/27/1998
• Issued: 08/15/2000
• Est. Priority Date: 07/08/1997
• Status: Expired due to Term

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Micron Technology, Inc.
• Inventors: Ahn, Kie Y., Forbes, Leonard, Noble, Wendell P.
• Primary Examiner(s): Meier, Stephen D.
• Application Number:
  US09/031,620
• Time in Patent Office: 900 Days
• Field of Search: 257/329, 257/330, 257/623
• US Class Current: 257/330
• CPC Class Codes: H10B 12/0383 wherein the transistor is vertical
• CPC Class Codes: H10B 12/395 the transistor being vertical

Abstract

An integrated circuit and fabrication method includes a vertical transistor for a memory cell in a dynamic random access memory (DRAM) or other integrated circuit. Vertically oriented access transistors are formed on semiconductor pillars on buried bit lines. Buried gates and body contacts are provided for each access transistor on opposing sides of the pillars. Buried word lines extend in first alternating trenches orthogonal to the bit lines. The buried word lines interconnect ones of the gates. Buried body lines extend in second alternating trenches orthogonal to the bit lines. The buried body lines interconnect body regions of adjacent access transistors. Unitary and split-conductor gate and body lines are provided for shared or independent signals to access transistors on either side of the trenches. In one embodiment, the memory cell has a surface area that is approximately 4 F², where F is a minimum feature size. Bulk-semiconductor and semiconductor-on-insulator (SOI) embodiments are provided.

Claims

1. An integrated circuit, comprising:

a pillar of semiconductor material that extends outwardly from a working surface of a substrate, the pillar having a number of sides; and

a transistor having a body region and first and second source/drain regions formed within the pillar, and having a gate and a body contact that are each associated with a side of the pillar.

2. The integrated circuit of claim 1, further comprising a storage capacitor coupled to the second source/drain diffusion.

3. The integrated circuit of claim 1, wherein the first source/drain region includes a more heavily doped bit line portion.

4. The integrated circuit of claim 1, wherein the pillar extends outwardly from an insulating portion of the substrate.

5. The integrated circuit of claim 1, wherein the pillar extends outwardly from a semiconductor portion of the substrate.

6. A memory device, comprising:

an array of memory cells, each cell comprising a transistor including a semiconductor pillar forming body and first and second source/drain regions, and a gate and a body contact disposed adjacent to opposing sides of the pillar,

a plurality of substantially parallel word lines, each word line disposed orthogonally to the bit lines in a trench between columns of the memory cells for addressing gates of the transistors of the memory cells that are adjacent to the trench in which the word line is disposed;

a plurality of substantially parallel body lines, interdigitated with the word lines, each body line disposed orthogonally to the bit lines in a trench between columns of the memory cells for providing a signal to body regions of the transistors of the memory cells that are adjacent to the trench in which the body line is disposed; and

a plurality of bit lines, proximal to the substrate, and interconnecting ones of the first source/drain regions of ones of the memory cells.

7. The memory device of claim 6, wherein each memory cell further comprises a storage capacitor coupled to the second source/drain diffusion.

8. The memory device of claim 6, wherein the pillars extend outwardly from an insulating portion of the substrate.

9. The memory device of claim 6, wherein the pillars extend outwardly from a semiconductor portion of the substrate.

10. The memory device of claim 6, wherein the integrated circuit surface area of the memory cell is 4F², where F is a minimum feature size.

11. An integrated circuit, comprising:

a pillar of semiconductor material that extends outwardly from a working surface of a substrate, the pillar having an upper surface and a number of sides; and

a transistor having a vertically stacked body and first and second source/drain regions formed within the pillar, and having a gate and a body contact that are each associated with a side of the pillar, wherein the gate and the body contact are located below the upper surface of the semiconductor pillar.

12. The integrated circuit of claim 11, wherein the gate and the body contact are associated with opposite sides of the pillar.

13. The integrated circuit of claim 11, including an insulating layer between the first source/drain region and an underlying semiconductor portion of the substrate.

14. A memory array comprising:

a plurality of substantially parallel bit lines at least partially on a substrate;

a plurality of memory cells, each memory cell including an access transistor having body and first and second source/drain regions vertically formed on one of the bit lines, the second source/drain region including an upper semiconductor surface;

a plurality of word lines and body lines, the word lines interconnecting gates of access transistors and the body lines interconnecting body regions of access transistors, the word and body lines interdigitated with each other and disposed orthogonally to the bit lines in isolation trenches, wherein the bit lines and the word and body lines are located below the upper semiconductor surface of the second source/drain region; and

a plurality of isolation trenches extending parallel to and between the bit lines, and interposed between ones of the access transistors.

15. The memory array of claim 14, wherein the bit lines include portions of the first source/drain regions of ones of the access transistors.

16. The memory array of claim 14, wherein the word line provides common gate regions for access transistors on opposing sides of the trench in which the word line is disposed.

17. The memory array of claim 14, wherein the body line provides common interconnection to body regions of access transistors on opposing sides of the trench in which the body line is disposed.

18. The memory array of claim 14, wherein the word line provides separate conductors for gate regions of access transistors on opposite sides of the trench in which the word line is disposed.

19. The memory array of claim 14, wherein the body line provides separate conductors for second gate regions of access transistors on opposite sides of the trench in which the second word line is disposed.

20. The memory array of claim 14, including an insulating layer interposed between the bit lines and a semiconductor portion of the substrate.

21. A memory array comprising:

a plurality of substantially parallel bit lines at least partially on a substrate;

a plurality of memory cells, each memory cell including an access transistor having body and first and second source/drain regions vertically formed on one of the bit lines, the second source/drain region including an upper semiconductor surface;

a plurality of word line pairs, each word line pair disposed in first trenches extending orthogonal to the bit lines, each word line in the word line pair separated from the other word line in the word line pair;

a plurality of body line pairs, each body line pair disposed in second trenches that are interdigitated with the first trenches, wherein the second trenches extend orthogonal to the bit lines, each body line in the body line pair separated from the other body line in the body line pair; and

a plurality of isolation trenches extending parallel to and between the bit lines, and interposed between ones of the access transistors.

22. The memory array of claim 21, wherein the bit lines, word line pairs, and body line pairs are located below the upper semiconductor surface of the second source/drain region.

23. The memory array of claim 21, including an insulating layer interposed between the bit lines and a semiconductor portion of the substrate.

24. The memory array of claim 21, wherein the bit lines include at least a portion of ones of the first source/drain regions.