Controlled linewidth reduction during gate pattern formation using an SiON BARC

• US 6,107,172 A
• Filed: 08/01/1997
• Issued: 08/22/2000
• Est. Priority Date: 08/01/1997
• Status: Expired due to Term

• Current Assignee: Advanced Micro Devices, Inc.
• Original Assignee: Advanced Micro Devices, Inc.
• Inventors: Yang, Chih-Yuh, Bell, Scott A., Steckert, Daniel
• Primary Examiner(s): Niebling, John F.
• Assistant Examiner(s): Jones, Josetta I.
• Application Number:
  US08/905,104
• Time in Patent Office: 1,117 Days
• Field of Search: 438/671, 438/636, 438/738, 438/951, 438/952, 438/585
• US Class Current: 438/585
• CPC Class Codes: H01L 21/32139 using masks
• CPC Class Codes: Y10S 438/951 Lift-off
• CPC Class Codes: Y10S 438/952 Utilizing antireflective layer

Abstract

A gate is formed by creating a wafer stack, that includes a gate conductive layer over a substrate layer, depositing a SiO_x N_y layer over the conductive layer to act as a bottom anti-reflective coating (BARC), and forming a resist mask on the SiO_x N_y layer. Next, the resist mask is isotropically etched to further reduce the critical dimensions of the gate pattern formed therein, and then the underlying BARC and wafer stack are etched to form a gate out of the conductive layer.

Claims

1. A method for forming a gate structure from a semiconductor wafer stack comprising a substrate and a conductive layer above the substrate, the method comprising:

depositing a SiO_x N_y layer on the conductive layer, wherein the SiO_x N_y layer is arranged to function as a bottom anti-reflective coating;

depositing a resist layer on the SiO_x N_y layer;

forming a first resist mask with the resist layer while using the SiO_x N_y layer as a bottom anti-reflective coating, wherein the first resist mask defines a first line having a first width;

isotropically etching the first resist mask to create a second resist mask, such that portions of the first line are removed to form a second line having a second width, wherein the second width is narrower than the first width;

etching through selected portions of the SiO_x N_y layer as defined by the second resist mask; and

etching through selected portions of the gate conductive layer as defined by the etched SiO_x N_y layer to form a gate from the gate conductive layer, wherein the gate has a gate width substantially equal to the second width, wherein

the SiO_x N_y layer is configured to attenuate interference waves produced in forming the first resist mask.

2. The method as recited in claim 1, wherein the gate conductive layer includes a polycrystalline silicon layer.

3. The method as recited in claim 1, wherein the first resist mask is formed using deep-UV waveforms and the SiO_x N_y layer attenuates interference waves having an approximate wavelength of 248 nm.

4. The method as recited in claim 1, wherein the step of isotropically etching the first resist mask to create a second resist mask includes a trim etch process in a plasma etching system.

5. The method as recited in claim 4, wherein a reactor within the plasma etching system is supplied with a mixture of gases including HBr and O₂.

6. The method as recited in claim 4, wherein a reactor within the plasma etching system is supplied with a mixture of gases including HBr and HeO₂.

7. The method as recited in claim 4, wherein a reactor within the plasma etching system is supplied with a mixture of gases including N₂, He and O₂.

8. The method as recited in claim 4, wherein a reactor within the plasma etching system is supplied with a mixture of gases including between approximately 10 to 60% HBr, 40 to 90% O₂, and 0 to 40% inert gas.

9. The method as recited in claim 8, wherein inert gas is selected from Ar and He.

10. The method as recited in claim 4, wherein the plasma etching system is a reactive ion etching system.

11. The method as recited in claim 10, wherein a reactor within the reactive ion etching system is supplied with a mixture of gases at a rate between approximately 40 and 150 sccm, during the trim etch process.

12. The method as recited in claim 10, wherein a reactor within the reactive ion etching system is supplied with a biasing power of between approximately 150 and 400 Watts, during the trim etch process.

13. The method as recited in claim 10, wherein a reactor within the reactive ion etching system has a pressure that is maintained at between approximately 20 and 150 mT, during the trim etch process.

14. The method as recited in claim 4, wherein the plasma etching system is a high density plasma etching system.

15. The method as recited in claim 10, wherein a reactor within the high density plasma etching system is supplied with a mixture of gases at a rate between approximately 50 and 170 sccm, during the trim etch process.

16. The method as recited in claim 10, wherein a reactor within the high density plasma etching system is supplied with a biasing power of between approximately 400 and 1000 Watts, during the trim etch process.

17. The method as recited in claim 10, wherein a reactor within the high density plasma etching system has a pressure that is maintained at between approximately 3 and 10 mT, during the trim etch process.

18. A method for forming a gate structure from a semiconductor wafer stack comprising a substrate and a conductive layer above the substrate, the method comprising:

depositing a SiO_x N_y layer on the conductive layer, wherein the SiO_x N_y layer is arranged to function as a bottom anti-reflective coating;

depositing a resist layer on the SiO_x N_y layer;

forming a first resist mask with the resist layer while using the SiO_x N_y layer as a bottom anti-reflective coating, wherein the first resist mask defines a first line having a first width;

isotropically etching the first resist mask to create a second resist mask, such that portions of the first line are removed to form a second line having a second width, wherein the second width is narrower than the first width;

etching through selected portions of the SiO_x N_y layer as defined by the second resist mask;

etching through selected portions of the gate conductive layer as defined by the etched SiO_x N_y layer to form a gate from the gate conductive layer, wherein the gate has a gate width substantially equal to the second width; and

removing the SiO_x N_y layer and the second resist mask from the gate.

19. A method for forming a gate on a semiconductor wafer using a bottom anti-reflective coating and a trim etch process, the method comprising:

creating a wafer stack by forming a gate conductive layer over a substrate, depositing a SiO_x N_y layer over the conductive layer to act as a bottom anti-reflective coating, and forming a resist mask on the SiO_x N_y layer;

isotropically etching the resist mask to reduce a width of a gate line pattern formed therein; and

shaping the wafer stack using the isotropically etched resist mask by sequentially etching through exposed portions of the SiO_x N_y layer and the gate conductive layer, wherein

the SiO_x N_y layer is configured to attenuate interference waves produced in forming the resist mask.