High performance embedded semiconductor memory device with multiple dimension first-level bit-lines

  • US 6,108,229 A
  • Filed: 07/13/1998
  • Issued: 08/22/2000
  • Est. Priority Date: 05/24/1996
  • Status: Expired due to Fees
First Claim
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1. A DRAM (dynamic random access memory) cell array supported on a substrate comprising:

  • a plurality of memory cells each having a select-transistor wherein each of said select-transistor having a select-transistor-gate;

    a peripheral logic-circuit having logic-transistors wherein each of said logic-transistors having a logic-transistor-gate;

    said select-transistor-gate and said logic-circuit-gate having substantially a same thickness;

    said select-transistor for each of said memory cells having a select-transistor threshold voltage and each of said logic-transistors of said peripheral logic-circuit having a logic-transistor threshold voltage wherein said select-transistor threshold voltage is substantially the same as said logic-transistor threshold voltage.

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