Body contacted dynamic memory

• US 6,111,778 A
• Filed: 05/10/1999
• Issued: 08/29/2000
• Est. Priority Date: 05/10/1999
• Status: Expired due to Fees

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: MacDonald, Eric, Mukherjee, Subir
• Primary Examiner(s): Nelms, David
• Assistant Examiner(s): Yoha, Connie C.
• Application Number:
  US09/307,865
• Time in Patent Office: 477 Days
• Field of Search: 365/149, 365/150, 365/185.01, 257/350
• US Class Current: 365/149
• CPC Class Codes: G11C 11/404 with one charge-transfer gate, e.g. MOS transistor, per cell
• CPC Class Codes: G11C 11/405 with three charge-transfer gates, e.g. MOS transistors, per cell
• CPC Class Codes: H01L 27/1203 the substrate comprising an insulating body on a semiconductor body, e.g. SOI three-dimensional layout H01L27/0688
• CPC Class Codes: H01L 29/7841 with floating body, e.g. programmable transistors
• CPC Class Codes: H10B 12/00 Dynamic random access memory [DRAM] devices
• CPC Class Codes: H10B 12/10 DRAM devices comprising bipolar components
• CPC Class Codes: H10B 12/33 the capacitor extending under the transistor

Abstract

A dynamic memory circuit in which the inherent bipolar transistor effect within a floating body transistor is utilized to store an information bit. A floating body of a storage transistor stores an information bit in the form of an electric charge. The floating body is charged and discharged via an access transistor during data write operations. The inherent bipolar transistor resident within the floating body transistor increases the effective capacitance of the floating body which acts as the storage node, and thereby enhances the magnitude of the discharge current which represents the stored information bit during read operations.

Claims

1. A dynamic memory circuit comprising:

a storage transistor having a body contacted by a body terminal, a gate terminal connected to a fixed potential, a source contacted by a source terminal, and a drain contacted by a drain terminal;

a read-word input coupled to said source terminal of said storage transistor;

a read-bit output coupled to said drain terminal of said storage transistor;

an access transistor having an access drain terminal coupled to said body terminal of said storage transistor, an access gate terminal, and an access source terminal;

p1 a write-word input coupled to said access gate terminal having at least two different operating potentials; and

a write-bit input coupled to said access source terminal.

2. The dynamic memory circuit of claim 1, wherein said body of said storage transistor is a floating body that stores an information bit in the form of an electric charge.

3. The dynamic memory circuit of claim 2, wherein said storage transistor is an SOI transistor.

4. The dynamic memory circuit of claim 2, wherein when said an electric charge accumulates within said body, said body functions as the base of an inherent bipolar transistor having an emitter corresponding to the source of said storage transistor, and a collector corresponding to the drain of said storage transistor, and wherein said emitter and said base form an emitter-base junction.

5. The dynamic memory circuit of claim 4, wherein said inherent bipolar transistor releases a discharge current on said read-bit output when said emitter-base junction is forward biased.

6. The dynamic memory circuit of claim 5, wherein said inherent bipolar transistor has a current gain equal to beta, and wherein the magnitude of said discharge current is proportional to the product of said stored electric charge multiplied by beta.

7. A dynamic memory cell comprising:

a storage silicon-on-insulator (SOI) field-effect transistor (FET) including;

an N-type source terminal;

an N-type drain terminal;

a P-type floating body contacting the N-type source terminal and the N-type drain terminal contact, wherein the P-type floating body stores an information bit, and wherein said P-type floating body comprises the base of an inherent bipolar transistor having an emitter that corresponds to said N-type source terminal, and a collector that corresponds to said N-type drain terminal, such that the P-type floating body and N-type source terminal form a PN junction that is biased in accordance with voltage differential between said RWL and the floating body charge;

a read word line (RWL) signal coupled to the N-type source terminal for accessing the information bit; and

a read bit line (RBL) signal coupled from the N-type drain terminal for detecting the information bit in response said RWL signal being applied to the N-type source terminal.

8. The dynamic memory cell of claim 7, wherein said P-type floating body stores an information bit in the form of a floating body charge.

9. The dynamic memory cell of claim 7, wherein said information bit is represented by a positive charge accumulation within said P-type floating body, and wherein said inherent bipolar transistor delivers said information bit onto said RBL by discharging said floating body through said N-type source terminal in response to a shifting logic level on said RWL that results in the PN junction formed by the P-type floating body and N-type source terminal becoming forward biased.

10. The dynamic memory cell of claim 9, wherein said discharging of said floating body through said N-type source terminal features a read current at said RBL that is proportional to the current gain of said inherent bipolar transistor multiplied by said floating body charge.

11. The dynamic memory cell of claim 7, further comprising a write access transistor having a terminal coupled to said floating body of said storage SOI FET, such that said information bit may be delivered from said access transistor to said storage transistor from which said information bit may be retrieved.

12. The dynamic memory cell of claim 7, further comprising a body contact for providing electrical access to said floating body of said storage SOI FET.

13. The dynamic memory cell of claim 7, wherein said storage SOI FET is a MOSFET transistor.