Separate byte control on fully synchronous pipelined SRAM

  • US 6,115,320 A
  • Filed: 02/23/1998
  • Issued: 09/05/2000
  • Est. Priority Date: 02/23/1998
  • Status: Expired due to Term
First Claim
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1. A synchronous random access memory system, comprising:

  • a memory having a memory structure for receiving an input data word to be written into the memory and for receiving an output data word from the memory, the input data word and the output data word each comprising at least two bytes, and the memory being capable of separately writing each byte of the input data word to an address in response to a set of at least two control signals and of outputting the output data word corresponding to the address;

    a set of input registers, comprising an input address register for storing an input address to which data is to be written into the memory or from which data is to be read from the memory system, anda set of input control registers for storing the at least two control signals for controlling the writing of data to the memory or the reading of data from the memory system;

    an address bus terminal coupled to the input address register for receiving the input address;

    a control terminal coupled to the input control registers for receiving the at least two control signals;

    a data structure for receiving a write data word to be written into the memory and for receiving a read data word which was read from the memory, the write data word and the read data word each consisting of at least two bytes; and

    a control logic which is coupled to the input registers to receive the input address from the input address register and the at least two control signals from the input control registers, the control logic also being coupled to the data structure such that the control logic receives the write data word to be written into the memory from the data structure and the data structure receives the read data word which was read from the memory system, the control logic also being coupled to the memory in order to send the input data word to the memory, receive the output data word from the memory, send the at least two control signals to the memory, and send the input address to the memory, the control logic comprisingat least one logic address register for storing an address to which data is to be written in the memory,a set of logic control registers for storing the at least two control signals,at least one data storage register for storing the write data word to be written into the memory,a write logic for regulating the presentation of the address, the control signals, and the write data word to the memory, the write logic being capable of detecting a read request and suspending presentation of a write command to the memory, anda read logic capable of detecting a read request on the input registers and choosing the read data word from bytes of data that are stored in the memory and from bytes of data that are stored in the control logic in order to send the data structure the read data word corresponding to the input address stored in the input address register.

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