Separate byte control on fully synchronous pipelined SRAM

• US 6,115,320 A
• Filed: 02/23/1998
• Issued: 09/05/2000
• Est. Priority Date: 02/23/1998
• Status: Expired due to Term

• Current Assignee: Integrated Device Technology Incorporated (Renesas Electronics Corporation)
• Original Assignee: Integrated Device Technology Incorporated (Renesas Electronics Corporation)
• Inventors: Mick, John R., Baumann, Mark W.
• Primary Examiner(s): Zarabian, A.
• Application Number:
  US09/028,206
• Time in Patent Office: 925 Days
• Field of Search: 365/233, 365/189.02, 365/230.02, 365/240, 365/189.12, 365/189.09, 365/230.08
• US Class Current: 365/189.18
• CPC Class Codes: G11C 11/419 Read-write [R-W] circuits

Abstract

A memory system including a memory array, an input circuit and a logic circuit is presented. The input circuit is coupled to receive a memory address and a set of individual write controls for each byte of data word. During a write operation, the input circuit also receives the corresponding write data to be written into the SRAM. The logic circuit causes the write data and write control information to be stored in the input circuit for the duration of any sequential read operations immediately following the write operation and then to be read into memory during a subsequent write operation. During the read operation, data which is stored in the write data storage registers prior to being read into the memory can be read out from the memory system should the address of one or more read operations equal the address of the data to be written into the memory while temporarily stored in the write data storage registers.

Claims

1. A synchronous random access memory system, comprising:

a memory having a memory structure for receiving an input data word to be written into the memory and for receiving an output data word from the memory, the input data word and the output data word each comprising at least two bytes, and the memory being capable of separately writing each byte of the input data word to an address in response to a set of at least two control signals and of outputting the output data word corresponding to the address;

a set of input registers, comprising an input address register for storing an input address to which data is to be written into the memory or from which data is to be read from the memory system, and

a set of input control registers for storing the at least two control signals for controlling the writing of data to the memory or the reading of data from the memory system;

an address bus terminal coupled to the input address register for receiving the input address;

a control terminal coupled to the input control registers for receiving the at least two control signals;

a data structure for receiving a write data word to be written into the memory and for receiving a read data word which was read from the memory, the write data word and the read data word each consisting of at least two bytes; and

a control logic which is coupled to the input registers to receive the input address from the input address register and the at least two control signals from the input control registers, the control logic also being coupled to the data structure such that the control logic receives the write data word to be written into the memory from the data structure and the data structure receives the read data word which was read from the memory system, the control logic also being coupled to the memory in order to send the input data word to the memory, receive the output data word from the memory, send the at least two control signals to the memory, and send the input address to the memory, the control logic comprising

at least one logic address register for storing an address to which data is to be written in the memory,

a set of logic control registers for storing the at least two control signals,

at least one data storage register for storing the write data word to be written into the memory,

a write logic for regulating the presentation of the address, the control signals, and the write data word to the memory, the write logic being capable of detecting a read request and suspending presentation of a write command to the memory, and

a read logic capable of detecting a read request on the input registers and choosing the read data word from bytes of data that are stored in the memory and from bytes of data that are stored in the control logic in order to send the data structure the read data word corresponding to the input address stored in the input address register.

2. The memory system of claim 1, wherein the data structure comprises:

a data input bus for receiving the write data word to be read into the memory; and

a data output bus for receiving the read data word to be read out from the memory system.

3. The memory system of claim 1, wherein the data structure comprises a data input/output bus terminal for receiving the write data word to be read into the memory and for also receiving the read data word to be read out from the memory system.

4. The memory system of claim 1 wherein in a write operation immediately following a read operation, the random access memory system is capable of storing in the memory write data received in the memory system prior to the read operation, the write data being stored at an address in the memory corresponding to an address stored in the at least one logic address registers.

5. The memory system of claim 1, wherein the memory structure includes:

an address port for receiving the address from the control logic;

a data-in port for receiving the input data word from the control logic;

a data-out port for sending the output data word to the control logic; and

a control port for receiving the control lines from the control logic.

6. The memory system of claim 5, wherein the control logic is capable of placing in the data storage registers the write data word to be written into the memory in conformance with the write operation and, in the read request immediately following the write operation, is capable of reading out the bytes of data from the output data word of the memory if the address requested is one not stored in the control logic or the byte is not one to be written into the memory, and from the control logic if the address is one stored in the logic circuit and that byte of the write data word is to be written into the memory.

7. A synchronous random access memory system, comprising:

a memory having a memory structure for receiving an input data word to be written into the memory and for receiving an output data word to be read out of the memory, the input data word and the output data word each consisting of at least two bytes, and the memory being capable of separately writing each byte of the input data word in response to a set of at least two control lines;

at least one data bus terminal for receiving a write data word to be written into the memory and for also receiving a read data word to be read out of the memory system, the write data word and the read data word each having at least two bytes;

an address bus terminal for receiving addresses for the write data word to be written into the memory and the read data word to be read out of the synchronous random access memory system; and

a control terminal for receiving at least two control signals indicating individually whether each byte of the write data word is to be written into the memory or whether each byte of the read data word is to be read from the memory system;

wherein,

in a read operation, the synchronous random access memory system is capable of providing the read data word at the at least one data bus terminal, the read data word corresponding to an address in the synchronous random access memory system,

in a write operation, the synchronous random access memory system is capable of storing the write data word received at the at least one data bus terminal, the write data word corresponding to an address in the synchronous random access memory system, and

in the read operation following the write operation, the synchronous random access memory system is capable of outputting to the at least one data bus terminal the read data word, the read data word being formed from bytes of the write data word that the control signals indicate are to be stored into the memory in combination with bytes of the output data word read from the memory corresponding to bytes of the write data word that the at least two control signals indicate are not to be stored into the memory.

8. The memory system of claim 7, wherein in a write operation following a read operation, the synchronous random access memory system is capable of storing in the memory the write data word previously stored in the memory system corresponding to an address previously received on the address bus terminal and stored in the memory system and in response to the control signals previously stored in the memory system.

9. The memory system of claim 8, wherein in a read operation immediately following a read operation, the synchronous random access memory system is capable of outputting at the data bus terminal, the read data word from a combination of bytes stored within the memory and bytes stored outside the memory of the synchronous random access memory system.

10. The memory system of claim 9, wherein in a write operation immediately following a write operation, the random access memory system is capable of storing in the memory the write data previously stored in the memory system in response to the control signals previously stored in the memory system.

11. The memory system of claim 10, wherein the memory structure includes:

an address port;

a data-in port for receiving the input-data word;

a data-out port for receiving the output-data word; and

a control port for receiving the control lines.

12. The memory system of claim 11 and further comprising:

a control circuit coupled to the address bus terminal, the at least one bus terminal, the control terminal, the address port, the data-in port, the data-out port, and the control port wherein during a write operation, the control circuit is capable of storing an address received from the address bus terminal, a control signal received from the control terminal, and write data corresponding to the address from the data input/output bus terminal.

13. The memory system of claim 12, wherein the control circuit is capable of storing the write data in the memory during a write operation following the write operation during which the address, the control signal and the write data were stored in the input circuit, and wherein the control circuit is not capable of storing the write data in the memory during a read operation immediately following the write operation during which the address, the control signal and the write data were stored in the input circuit.

14. The memory system of claim 13 and further comprising:

a selection logic circuit coupled to the control circuit and the memory, wherein the selection logic circuit is capable of causing the random access memory system to output those bytes of the write data stored in the input circuit which are to be written into the memory when, during a read operation, the address of the read operation matches the address stored in the input circuit.

15. The memory system of claim 14, wherein the control circuit comprises:

an input address register having an input port and an output port, the input port being coupled to the address bus terminal;

a logic address register having an input port coupled to the output port of the input register and an output port coupled to the selection logic circuit;

an input control register having an input terminal coupled to the control terminal and an output terminal coupled to the selection logic circuit; and

a data register having an input port coupled to the at least one bus terminal for receiving the write data word and an output port coupled to the data-in port of the memory and to the selection logic circuit.

16. The memory system of claim 15, wherein the selection logic circuit comprises:

an address multiplexer having

a first input port coupled to the output port of the input address register;

a second input port coupled to the output port of the logic address register; and

an output port coupled to the address port of the memory;

a write enable circuit having an input terminal coupled to the output terminal of the input control register and having an output terminal coupled to the control port of the memory;

at least two output data multiplexers, each corresponding to one byte of the read word, each of the output data multiplexers having

a first input port coupled to the corresponding byte of the output data word at the data-out port of the memory,

a second input port coupled to the corresponding byte of the write data word at the data register,

an output port coupled to the corresponding byte of the read data word at the at least one bus terminal, and

an input-select port which controls whether the first input port or the second input port of the output data multiplexer is coupled to the output port of the output data multiplexer;

at least two logic gates, corresponding to each of the output data multiplexers, each of the logic gates having a first input, a second input and an output, the first input being coupled to the output of the control signal corresponding to that byte of the write data word, and the output being coupled to the input-select port of the data multiplexer which corresponds to that byte of the read data word; and

a comparator having a first input port coupled to the output port of the input address register, a second input port coupled to the output port of the logic address register, and an output port coupled to second input of each of the logic gates;

wherein the logic gates choose each individual byte of data to be read out of the memory system depending on whether the byte is stored in the control circuit or in the memory.

17. A synchronous random access memory system, comprising:

a memory array having;

an address port for receiving addresses for data to be written into or read from the memory array, the data having at least two bytes;

a control port for receiving write and read signals to cause data to be written into and read from the memory array, the data having at least two bytes and the write signals also indicating which bytes of the data are to be written into the memory array;

a data-in port for receiving data being written into the memory array; and

a data-out port for outputting data being read out of the memory array;

a logic circuit;

a set of input registers, including;

an input address register for receiving an address corresponding to a write or read signal, the input address register having an output bus coupled by the logic circuit to the address port of the memory array; and

a set of input control registers for receiving a set of write signals or read signals, the write signals indicating which bytes of data are to be written into the memory array, the input control registers having an output terminal coupled by the logic circuit to the control port;

at least one data bus for receiving data to be written into or read out of the memory system, the at least one data bus being coupled by the logic circuit to the data-out port of the memory array; and

a first data register having an input bus coupled to the at least one data bus and an output bus coupled by the logic circuit to the data-in port.

18. The memory system of claim 17, wherein the logic circuit includes:

a logic address register for receiving an address from the input address register, the logic address register having an input bus coupled to the output bus of the input address register and an output bus;

a logic control register for receiving control signals from the input control register, the logic control register having an input bus coupled to the output bus of the input control register and an output bus; and

a first comparator for comparing a first address in the input address register to a second address in the logic address register, and for producing a first signal if the first address equals the second address and for producing a second signal if the first address does not equal the second address.

19. The memory system of claim 18, wherein the logic circuit further includes:

a first multiplexer circuit having at least two first multiplexers, each first multiplexer for passing a corresponding byte of data stored in the first data register to the at least one data bus in response to a read signal in the input control registers when the first address equals the second address and the write signals indicate that the byte of data is to be stored in the memory array.

20. The memory system of claim 19, wherein the logic circuit includes:

a second multiplexer circuit for passing the first address to the address port when the input control register contains a read signal and for passing the second address to the address port when the input control register contains a write signal.

21. The memory system of claim 20, wherein the logic circuit includes:

an output buffer between the second multiplexer circuit and the at least one data bus.

22. The memory system of claim 21, wherein the output buffer is capable of assuming a high impedance or low impedance.

23. The memory system of claim 20, wherein the output buffer is a tristate buffer.

24. The memory system of claim 18, wherein the logic circuit includes:

a second logic address register having an input bus and an output bus, the input bus coupled to the output bus of the logic address register;

a second logic control register having an input bus and an output bus, the input bus coupled to the output bus of the logic control register, the output bus being coupled to the control port of the memory array; and

a second comparator for comparing the first address in the input address register to a third address in the second logic address register, and for producing a first signal if the first address equals the third address and for producing a second signal if the first address does not equal the second address.

25. The memory system of claim 24, wherein the logic circuit includes a first multiplexer having a first input coupled to the output of the input address register, a second input coupled to the output of the second logic address register and an output coupled to the address port of the memory array.

26. The memory system of claim 25, wherein the logic circuit includes a second data register having an input bus coupled to the output bus of the first data register and an output bus coupled to the data-in port of the memory array.

27. The memory system of claim 26, wherein the logic circuit includes a second multiplexer for passing data on the first output register to the data-in port of the memory array or for passing data on the second output register to the data-in port of the memory array in response to a third input select signal.

28. The memory system of claim 27, further including an output register having an input bus and an output bus, the input bus being separable into at least two bytes and being coupled to the data-out port of the memory array, to the output bus of the first data register, to the output bus of the second data register and to the at least one data bus of the memory system.

29. The memory system of claim 28, wherein the logic circuit includes an output selection circuit coupled to the input bus of the output register, the output selection circuit being also coupled to the data-out port of the memory array, to the output bus of the first data register, to the output bus of the second data register and to the at least one data bus and the output selection circuit additionally coupled to the outputs of the first comparator, the second comparator, the logic control register and the second logic control register, the output selection circuit being capable of choosing individual bytes from the data-out port of the memory array, the output bus of the first data register, the output bus of the second data register and the at least one data bus for reading out to the output register.

30. The memory system of claim 29, wherein the output selection circuit comprises:

a first selection circuit, having

a first selection multiplexer circuit, having a first input, a second input, an output and an input select, the first input being coupled to the data-out port of the memory array, the second input being coupled to the output bus of the second data register, the first selection multiplexer capable of independently choosing at least two bytes from the data-out port of the memory array or the output bus of the second data register, and

a first selection logic circuit coupled to the input select of the first selection multiplexer circuit and also coupled with the outputs of the first comparator, the second comparator, the output port of the logic control register and the output port of the second logic control register;

a second selection circuit, having

a second selection multiplexer circuit having, a first input, a second input, an output and an input select, the first input being coupled to the output of the first selection multiplexer circuit, the second input being coupled to the output bus of the first data register, the second selection multiplexer capable of independently choosing at least two bytes from the output of the first selection multiplexer or the output bus of the first data register, and

a second selection logic circuit coupled to the input select of the second selection multiplexer circuit and also coupled with the outputs of the first comparator, the second comparator, the output port of the logic control register and the output port of the second logic control register; and

a third selection circuit, having

a third selection multiplexer circuit having a first input, a second input, an output and an input select, the first input being coupled to the output of the second selection multiplexer circuit, the second input being coupled to the at least one data bus, the second selection multiplexer capable of independently choosing at least two bytes from the output of the second selection multiplexer or the at least one data bus, the output of the third selection multiplexer circuit is coupled to the input bus of the output register, and

a third selection logic circuit coupled to the input select of the second selection multiplexer circuit and also coupled with the outputs of the first comparator, the second comparator, the output port of the logic control register and the output port of the second logic control register.