I/O and memory bus system for DFPs and units with two- or multi-dimensional programmable cell architectures

DC CAFC
  • US 6,119,181 A
  • Filed: 10/08/1997
  • Issued: 09/12/2000
  • Est. Priority Date: 12/20/1996
  • Status: Expired due to Term
First Claim
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1. A bus system, comprising:

  • a processing unit, the processing unit having a multi-dimensional programmable cell architecture;

    a first plurality of individual lines positioned within the processing unit, the first plurality of individual lines being bundled;

    at least one interface unit coupled to the plurality of individual lines, the at least one interface unit combining the first plurality of individual lines to form the bus system, the first plurality of individual lines providing communication, via the at least one interface unit, between the processing unit and at least one of;

    i) an additional processing unit, ii) a memory device, and iii) a peripheral device; and

    at least one state machine for controlling the at least one interface unit.

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