Memory device having plurality of flash memories with a flash memory controlling circuit
First Claim
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1. A memory device for use in a system providing mass data, comprising:
- connector means including a small computer system interface (SCSI) for connecting said memory device to the system;
a plurality of flash memories;
direct memory access (DMA) controller means connected to said connector means via an address bus, a control bus and a data bus, and to said flash memories via said data bus, for controlling data access and transmission therebetween; and
flash memory control circuit means connected to said data bus, said address bus said control bus and said flash memories for writing and reading data to and from the flash memories by page.
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Abstract
A memory device with a small computer system interface reads and writes mass data at high speed. The memory device includes a plurality of flash memories and a control circuit for allowing the flash memories to write and read data by page and to erase the data by block.
34 Citations
52 Claims
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1. A memory device for use in a system providing mass data, comprising:
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connector means including a small computer system interface (SCSI) for connecting said memory device to the system; a plurality of flash memories; direct memory access (DMA) controller means connected to said connector means via an address bus, a control bus and a data bus, and to said flash memories via said data bus, for controlling data access and transmission therebetween; and flash memory control circuit means connected to said data bus, said address bus said control bus and said flash memories for writing and reading data to and from the flash memories by page. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 37, 38, 39, 40, 41, 42, 43, 44, 45, 46)
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19. A memory device for use in a system providing mass data, comprising:
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connector means including a small computer system interface (SCSI) for connecting said memory device to the system; a plurality of flash memories; and flash memory control circuit means connected to said connector means and to said plurality of flash memories for transferring data between said system and said flash memories; wherein said flash memory control circuit means comprises a decoder for decoding address signals, and for outputting decoded signals, said decoder being enabled in response to a selection signal provided by said address decoder means. - View Dependent Claims (20, 21)
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22. A memory device for use in a system providing mass data, comprising:
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connector means including a small computer system interface (SCSI) for connecting said memory device to the system; a plurality of flash memories; flash memory control circuit means connected to said connector means and to said plurality of flash memories for transferring data between said system and said flash memories; and address decoder means connected to said connector means and to said flash memory control circuit means for decoding an address signal received through an address bus, and for transmitting decoded output signals to at least one of said connector means and said flash memory control circuit means; wherein said flash memory control circuit means further comprises a decoder circuit and an inverter connected thereto, said inverter being connected to said address decoder means for receiving and inverting a selection signal therefrom. - View Dependent Claims (23, 24, 25)
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26. A memory device for use in a system providing mass data, comprising:
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connector means including a small computer system interface (SCSI) for connecting said memory device to the system; a plurality of flash memories; and flash memory control circuit means connected to said connector means and to said plurality of flash memories for transferring data between said system and said flash memories; wherein said flash memory control circuit means comprises a decoder circuit producing an output signal, and an inverter circuit for receiving and inverting said output signal from said decoder circuit so as to generate a command latch enable signal.
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27. A method for auxiliary storage of mass data provided by a system via a small computer system interface (SCSI), comprising the steps of:
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providing a plurality of flash memories for the auxiliary storage of the mass data; selecting one of said flash memories, said selected one of said flash memories having a base address; latching at least one address by incrementing the base address by a given value; performing a desired data operation; and releasing one of the flash memories by setting the base address to a predetermined value. - View Dependent Claims (28, 29, 30, 31, 32, 33, 34, 35, 36, 47, 48, 49, 50, 51, 52)
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Specification