System for optimizing the testing and repair time of a defective integrated circuit
First Claim
1. An apparatus for testing a plurality of integrated circuits, said apparatus comprising:
- a testing device for performing a plurality of tests on said plurality of integrated circuits, each of said plurality of integrated circuits having a unique circuit identifier; and
a processor to control said testing device, said processor identifying each of said plurality of integrated circuits that failed at least one of said plurality of tests and identifying tests failed by each of said plurality of integrated circuits,wherein said testing device repeats at least one identified failed test on each integrated circuits that failed at least one of said plurality of tests.
5 Assignments
0 Petitions
Accused Products
Abstract
A method and apparatus for testing semiconductor memory chips, such as DRAMs, having a plurality of memory cells or bits. Each memory chip has a unique identifier stored in a database. Tests are performed on the memory chips and when a memory chip fails a test, the memory chip is placed in a repair bin and a test identifier is stored in the database in association with the memory chip identifier. In order to repair the memory chip, failed tests are read out of the database and such tests are again performed on the failed memory chip in order to determine which memory cell in the memory chip is faulty. The failed memory cells are then repaired.
28 Citations
13 Claims
-
1. An apparatus for testing a plurality of integrated circuits, said apparatus comprising:
-
a testing device for performing a plurality of tests on said plurality of integrated circuits, each of said plurality of integrated circuits having a unique circuit identifier; and a processor to control said testing device, said processor identifying each of said plurality of integrated circuits that failed at least one of said plurality of tests and identifying tests failed by each of said plurality of integrated circuits, wherein said testing device repeats at least one identified failed test on each integrated circuits that failed at least one of said plurality of tests. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13)
-
Specification