Power IC having SOI structure

• US 6,130,458 A
• Filed: 03/27/1997
• Issued: 10/10/2000
• Est. Priority Date: 03/28/1996
• Status: Expired due to Fees

• Current Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Original Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Inventors: Takagi, Yosuke, Endo, Koichi
• Primary Examiner(s): Thomas, Tom
• Assistant Examiner(s): Nadav, Ori
• Application Number:
  US08/828,028
• Time in Patent Office: 1,293 Days
• Field of Search: 257/139, 257/341, 257/347, 257/350, 257/351, 257/352, 257/354
• US Class Current: 257/351
• CPC Class Codes: H01L 21/743 Making of internal connections, substrate contacts
• CPC Class Codes: H01L 27/1203 the substrate comprising an insulating body on a semiconductor body, e.g. SOI three-dimensional layout H01L27/0688
• CPC Class Codes: H01L 29/7317 Bipolar thin film transistors
• CPC Class Codes: H01L 29/7394 on an insulating layer or substrate, e.g. thin film device or device isolated from the bulk substrate H01L29/7398 takes precedence
• CPC Class Codes: H01L 29/7824 with a substrate comprising an insulating layer, e.g. SOI-LDMOS transistors

Abstract

The present invention relates in general to power ICs, etc. having the SOI structure, and more specifically to the structure in which an SOI substrate comprises a base substrate, an SOI oxide film formed on the base substrate, and active layers formed on the SOI oxide film, and also integrates on itself power devices and the corresponding control elements monolithically. Between this base substrate and this SOI oxide film is formed heavily-doped semiconductor regions having a conductivity type opposite to that of this base substrate. Hence, the junction capacitance between the base substrate and the heavily-doped semiconductor regions decreases an actual capacitance between the base substrate and the active layer so that to inhibit or prevent inversion layers from being formed at the bottom of the active layers.

Claims

1. A power IC having high-side and low-side circuits connected in series, a connection point between the high-side and low-side circuits oscillating between predetermined voltage levels, the high-side circuit having a high-side power element and a high-side control circuit for providing a high-side control signal to the high-side power element, the low-side circuit having a low-side power element and a low-side control circuit for providing a low-side control signal independent from the high-side control signal to the low-side power element, higher voltage being applied to the high-side power element than that applied to the low-side power element the power IC comprising:

a first semiconductor region which acts as a base substrate;

an insulator film formed on the first semiconductor region;

a second semiconductor region formed on top of the insulator film so as to form a SOI structure with said first semiconductor region and insulator flim, the SOI structure serving as a first capacitor;

element isolation regions devising said second semiconductor region into dielectrically isolated first, second, third, and fourth active layers, so as to form said high-side power element, high-side control circuit, low-side power element, and low-side control circuit therein, respectively;

a third semiconductor region having a conductivity type opposite to that of the first semiconductor region, selectively disposed in vicinity of a boundary between the first semiconductor region and the insulator film, and disposed at a top surfaces of the first semiconductor region, the third semiconductor region having a specific impurity concentration and diffusion depth so as to develop a large width depletion layer between said third and first semiconductor regions such that a second capacitor being connected between said third and first semiconductor regions, the second capacitor being connected to said first capacitor so that the second capacitor suppresses generations of inversion layers, which tend to be formed at bottoms of said first and second active layers at floating potentials, the bottoms being contacted with the insulator film, said first capacitor being connected between said third and second semiconductor regions;

a groove which starts at a top surface of said first active layer, penetrates through said first active layer and said insulator film, and reaches said third semiconductor region;

a high-conductivity region formed inside the groove;

a fourth semiconductor region formed in a part of a top surface of said first active layer, the fourth semiconductor region being connected to said connection point; and

a surface wiring configured to connect said high-conductivity region with said fourth semiconductor region.

2. The power IC of claim 1, wherein said first and second semiconductor regions are opposite to each other in conductivity type.

3. The power IC of claim 1, wherein said first and second semiconductor regions have the same conductivity type.

4. The power IC of claim 1, wherein said third semiconductor region is formed throughout on the top surface of said first semiconductor region.

5. The power IC of claim 2, wherein said third semiconductor region is formed just under a whole bottom surface of one of said first, second, third and fourth active layers.

6. The power IC of claim 1, further comprising a fifth semiconductor region formed between said fourth semiconductor region and said first active layer.

7. The power IC of claim 1, wherein said fourth semiconductor region is one of two main electrodes of a high-blocking voltage power element which acts as said high-side power element.

8. The power IC of claim 7, wherein said high-blocking voltage power element is a Lateral Double-diffused MOSFET (LDMOSFET).

9. The power IC of claim 8, wherein said one of the two main electrodes is a source region.

10. The power IC of claim 7, wherein said high-blocking voltage power element is an Insulated Gate Bipolar Transistor (IGBT).

11. The power IC of claim 10, wherein said one of the two main electrodes is an emitter region.

12. The power IC of claim 1, wherein said third semiconductor region are divided into mutually independent regions, each independent region is arranged throughout under the first active layer and the second active layer, respectively.

13. The power IC of claim 1, wherein said third semiconductor region is formed as a common region throughout below the first and second active layers.

14. The power IC of claim 1, wherein

said third semiconductor region is selectively formed only below said high-side circuit.

15. A power device having high-side and low-side circuits connected in series, a connection point between said high-side and low-side circuits oscillating between predetermined voltage levels, the high-side circuit having a high-side power element and a high-side control circuit for providing a high-side control signal to the high-side power element, the low-side circuit having a low-side power element and a low-side control circuit for providing a low-side control signal independent from the high-side control signal to the low-side power element, higher voltage being applied to the high-side power element than that applied to the low-side power element, the power device comprising:

(a) a first semiconductor chip having the high-side and low side control circuits are merged in, comprising;

a first semiconductor region which acts as a base substrate;

an insulator film formed on top of the first semiconductor region;

a second semiconductor region formed on top of the insulator film so as to form a SOI structure with said first semiconductor region and insulator film, the SOI structure serving as a first capacitor;

element isolation regions dividing said second semiconductor region into dielectrically isolated high-side and low-side active layers, so as to form said high-side control circuit and low-side control circuit therein respectively;

a third semiconductor region, having a conductivity type opposite to that of said first semiconductor region formed in vicinity of a boundary between the first semiconductor region and the insulator film and in a top surface of the first semiconductor region, the third semiconductor region having a specific impurity concentration and diffusion depth so as to develop a large width depletion layer between said third and first semiconductor regions such that a second capacitor being connected between said third and first semiconductor regions, the second capacitor being connected to said first capacitor so that the second capacitor suppresses generation of an inversion layer, which tends to be formed at a bottom of said high-side active layer, said first capacitor being connected between said third and second semiconductor regions;

a groove which starts at a top surface of said high-side active layer and penetrates through said high-side active layer and said insulator film and reaches said third semiconductor region;

a high-conductivity region buried inside the groove,

a fourth semiconductor region formed in a part of a top surface of said high-side active layer, the fourth semiconductor region being connected to said connection point; and

a surface wiring configured to connect said high-conductivity region with said fourth semiconductor region, and

(b) a second semiconductor chip for merging the high-side power element.

16. The power device of claim 15, wherein said high-side control circuit and said high-side output element are formed on different semiconductor chips.