Architecture and methods for a hardware description language source level debugging system

• US 6,132,109 A
• Filed: 06/03/1994
• Issued: 10/17/2000
• Est. Priority Date: 04/12/1994
• Status: Expired due to Term

• Current Assignee: Synopsys Incorporated
• Original Assignee: Synopsys Incorporated
• Inventors: Lin, Jing C., Seawright, Andrew, Gregory, Brent, Chatterjee, Trinanjan, Raghvendra, Srinivas, Girczyc, Emil, Estrada, Paul
• Primary Examiner(s): Hafiz, Tariq R.
• Assistant Examiner(s): PENDER JR, MICHAEL J
• Application Number:
  US08/253,470
• Time in Patent Office: 2,328 Days
• Field of Search: 395/700, 395/701, 395/704, 395/705, 364/578, 364/488, 364/489, 364/490, 364/491
• US Class Current: 717/131
• CPC Class Codes: G06F 2119/12 Timing analysis or timing optimisation
• CPC Class Codes: G06F 30/30 Circuit design
• CPC Class Codes: G06F 30/33 Design verification, e.g. functional simulation or model checking
• CPC Class Codes: G06F 30/3308 using simulation

Abstract

This invention provides a method for displaying circuit analysis results corresponding to parts of the circuit near the portion of the hardware description language (HDL) specification that generated that part of the circuit. The invention also includes a method for using probe statements in the HDL specification to mark additional points in the initial circuit that should not be eliminated during optimization. This improves the ability to display circuit analysis results near the appropriate part of the HDL specification.

Claims

1. A method, comprising:

translating a synthesis source text file to an initial circuit including one or more parts connected together with nets;

identifying each part of said initial circuit with the portion of said synthesis source text file that created said part of said initial circuit;

optimize said initial circuit to produce a final circuit containing one or more parts connected together with nets;

analyzing said final circuit to determine characteristics associated with said final circuit'"'"'s parts and with said final circuit'"'"'s nets;

identifying said final circuit'"'"'s part'"'"'s that correspond directly with said initial circuit'"'"'s initial parts;

identifying said final circuit'"'"'s nets that correspond directly with said initial circuit'"'"'s nets; and

displaying said characteristics associated with those said final circuit'"'"'s nets and parts that correspond directly with said initial circuit'"'"'s nets and parts near said portions of said synthesis source text file that created said corresponding initial circuit parts and nets.

2. The method of claim 1 wherein said source text file includes directives indicating the location of probes and wherein said translating step include generating initial circuit parts or initial circuit nets that will correspond directly with said final circuit parts or final circuit nets.