Asynchronous transfer mode exchange system

• US 6,144,635 A
• Filed: 07/17/1997
• Issued: 11/07/2000
• Est. Priority Date: 07/18/1996
• Status: Expired due to Fees

• Current Assignee: NEC Corporation
• Original Assignee: NEC Corporation
• Inventors: Nakagawa, Tatsuo
• Primary Examiner(s): TON, DANG T
• Application Number:
  US08/896,025
• Time in Patent Office: 1,209 Days
• Field of Search: 370/229, 370/230, 370/231, 370/232, 370/233, 370/234, 370/235, 370/236, 370/395, 370/411, 370/412, 370/413, 370/414, 370/415, 370/416, 370/417, 370/418, 370/252, 370/241
• US Class Current: 370/229
• CPC Class Codes: H04L 2012/5635 Backpressure, e.g. for ABR
• CPC Class Codes: H04L 2012/5682 Threshold; Watermark
• CPC Class Codes: H04L 2012/5683 for avoiding head of line blocking
• CPC Class Codes: H04L 49/30 Peripheral units, e.g. input or output ports
• CPC Class Codes: H04L 49/3081 ATM peripheral units, e.g. policing, insertion or extraction
• CPC Class Codes: H04L 49/50 Overload detection or protection within a single switching element

Abstract

An asynchronous (ATM) exchange system comprises a plurality of input buffers each for receiving data cells from an input cell highway to temporarily store the data cells, a plurality of output buffers each for temporarily storing data cells to transmit the data cells to an output cell highway, and an array of ATM switches each for transferring data cells from one of the input buffers to one of the output buffers. The amount of data cells stored in each output buffer is monitored by an output buffer monitor and used for controlling the transfer rate of the data cells from each input buffers, thereby increasing durability of the ATM exchange system against a burst signal or buffer congestion.

Claims

1. An asynchronous transfer mode (ATM) exchange system comprising:

a plurality of input buffers each for receiving data cells from an input cell highway to temporarily store the data cells;

a plurality of output buffers each for temporarily storing data cells to transmit the data cells to an output cell highway;

an array of ATM switches each for transferring the data cells from a corresponding one of said input buffers to a corresponding one of said output buffers;

an output buffer monitor circuit for monitoring the amount of data cells stored in each of said output buffers to generate a cell amount signal representing the amount of data cells stored in the each of said output buffers; and

a cell output control circuit for receiving said cell amount signal to control a transfer rate of the data cells transferred from said input buffers based on said cell amount signal,

wherein said cell output control circuit increases and decreases the transfer rate of each of said input buffers in accordance with a decrease or increase of the amount of data cells stored in a corresponding one of said output buffers.

2. An asynchronous transfer mode exchange system comprising:

a plurality of input buffers each for receiving data cells from an input cell highway to temporarily store the data cells;

a plurality of output buffers each for temporarily storing data cells to transmit the data cells to an output cell highway;

an array of ATM switches each for transferring the data cells from a corresponding one of said input buffers to a corresponding one of said output buffers;

an output buffer monitor circuit for monitoring the amount of data cells stored in each of said output buffers to generate a cell amount signal representing the amount of data cells stored in the each of said output buffers; and

a cell output control circuit for receiving said cell amount signal to control a transfer rate of the data cells transferred from said input buffers based on said cell amount signal,

wherein the cell output control circuit controls the transfer rate of the data cells in the corresponding one of said input buffers in accordance with an inverse proportion of the amount of data cells stored in the corresponding one of said output buffers, as obtained from said cell amount signal.

3. An ATM exchange system as defined in claim 2, wherein, when the amount of data cells stored in the corresponding one of said output buffers decreases based on information obtained from said cell amount signal, the transfer rate of the data cells output from the corresponding one of said input buffers increases, and

wherein, when the amount of data cells stored in the corresponding one of said output buffers increases based on information obtained from said cell amount signal, the transfer rate of the data cells output from the corresponding one of said input buffers decreases.

4. An ATM exchange system as defined in claim 3, wherein an amount of increase of data cells stored in the corresponding one of said cell output buffers, as determined from comparing information in said cell amount signal at a first time and said cell amount signal at a second time later than the first time, is the same as an amount of decrease in the transfer rate of the data cells output from the corresponding one of said input buffers, as controlled by said cell output control circuit.

5. An ATM exchange system as defined in claim 4, wherein an amount of decrease of data cells stored in the corresponding one of said cell output buffers, as determined from comparing information in said cell amount signal at a third time and said cell amount signal at a fourth time later than the third time, is the same as an amount of increase in the transfer rate of the data cells output from the corresponding one of said input buffers, as controlled by said cell output control circuit.

6. An asynchronous transfer mode (ATM) exchange system comprising:

a plurality of input buffers each for receiving data cells from an input cell highway to temporarily store the data cells;

a plurality of output buffers each for temporarily storing data cells to transmit the data cells to an output cell highway;

an array of ATM switches each for transferring the data cells from a corresponding one of said input buffers to a corresponding one of said output buffers;

an output buffer monitor circuit for monitoring the amount of data cells stored in each of said output buffers to generate a cell amount signal representing the amount of data cells stored in the each of said output buffers; and

a cell output control circuit for receiving said cell amount signal to control a transfer rate of the data cells transferred from said input buffers based on said cell amount signal,

wherein said cell amount signal is outputted periodically by said output buffer monitor circuit irrespective as to whether or not any of said input buffers are outputting data to any of said output buffers.