CMOS static random access memory devices

• US 6,147,385 A
• Filed: 12/22/1998
• Issued: 11/14/2000
• Est. Priority Date: 12/23/1997
• Status: Expired due to Term

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Samsung Electronics Co. Ltd.
• Inventors: Kim, Sung-Bong, Youn, Jong-Mil, Kim, Ki-Joon
• Primary Examiner(s): Monin, Jr., Donald L.
• Application Number:
  US09/218,819
• Time in Patent Office: 693 Days
• Field of Search: 257/903, 257/369, 257/385, 257/351, 257/377, 257/382, 257/390, 257/368, 257/393, 365/156, 365/182, 365/180
• US Class Current: 257/369
• CPC Class Codes: H10B 10/00 Static random access memory [SRAM] devices
• CPC Class Codes: H10B 10/12 comprising a MOSFET load element
• CPC Class Codes: Y10S 257/903 FET configuration adapted for use as static memory cell

Abstract

A full CMOS SRAM cell having the capability of having a reduced aspect ratio is described. The SRAM cell includes first and second transfer transistors of n-channel types, first and second driving transistors of the n-channel types and first and second load transistors of p-channel types. Each of the transistors has source and drain regions on opposite sides of a channel region formed in a semiconductor substrate and a gate over the channel region. The cell includes a first common region defined by the drain regions of the first transfer transistor and the first driving transistor connected in series therethrough. A second common region is defined by the drain regions of the second transfer transistor and the second driving transistor connected in series therethrough. The drain region of the first load transistor is disposed adjacent to the first common region between the first and second common regions. The drain region of the second load transistor is disposed between the drain region of the first load transistor and the second common region. First and second gate electrode layers are disposed generally parallel to each other, and respectively serving as the gates of the first driving transistor and the first load transistor and as the gates of the second driving transistor and the second load transistor, wherein each of the first and second gate electrode layers is made of a conductive material of a first level. First and second interconnecting layers are each made of a conductive material of a second level different from the first level, the first interconnecting layer connecting the first common region to the drain region of the first load transistor and the second gate electrode layer, the second interconnecting layer connecting the second common region to the drain region of the second load transistor and the first gate electrode layer.

Claims

1. A static random access memory cell including first and second transfer transistors of n-channel type, first and second driving transistors of the n-channel type and first and second load transistors of p-channel type, each of said transistors having source and drain regions on opposite sides of a channel region formed in a semiconductor substrate and a gate over the channel region, said cell comprising:

a first common region defined by the drain regions of said first transfer transistor and said first driving transistor connected in series therethrough;

a second common region defined by the drain regions of said second transfer transistor and said second driving transistor connected in series therethrough;

the drain region of said first load transistor disposed adjacent said first common region between said first and second common regions;

the drain region of said second load transistor disposed between the drain region of said first load transistor and said second common region;

first and second gate electrode layers disposed generally parallel to each other, said first gate electrode layer serving as the gates of said first driving transistor and said first load transistor and said second gate electrode layer serving as the gates of said second driving transistor and said second load transistor, each of said first and second gate electrode layers being made of a conductive material at a first level of said memory; and

first and second interconnecting layers each made of a conductive material at a second level of said memory cell different from said first level, said first interconnecting layer connecting said first common region to the drain region of said first load transistor and to said second gate electrode layer, said second interconnecting layer connecting said second common region to the drain region of said second load transistor and to said first gate electrode layer.

2. The memory cell as recited in claim 1, further comprising:

isolation regions formed in said substrate;

first and second active regions separately formed in said substrate so as to be isolated by said isolation regions, each of said first and second active regions extending in a first direction, said first active region providing the source and channel regions and said first common region of said first transfer transistor and said first driving transistor, said second active region providing the source and channel regions and said second common region of said second transfer transistor and said second driving transistor;

third and fourth active regions separately formed in said substrate so as to be isolated by said isolation regions, said third active region extending from said drain region of said first load transistor in the first direction to provide the drain, channel and source regions thereof, said fourth active region extending to said drain region of said second load transistor in the first direction to provide the source, channel and drain regions thereof.

3. The memory cell as recited in claim 2, wherein each of said first and second active regions is a p-type well region formed in said substrate and each of said third and fourth regions is an n-type well region formed in said substrate.

4. The memory cell as recited in claim 2, wherein said first and second gate electrode layers extend in a second direction generally perpendicular to said first direction, one end portion of said first gate electrode layer being adjacent to said drain region of said second load transistor and one end portion of said second gate electrode layer being adjacent to said drain region of said first load transistor.

5. The memory cell as recited in claim 1, wherein said first transfer transistor, said first driving transistor and said first load transistor are respectively disposed generally symmetrically with said second transfer transistor, said second driving transistor and said second load transistor relative to a certain axis in said substrate.

6. The memory cell as recited in claim 1, wherein said first gate electrode layer is disposed generally symmetrically with said second gate electrode layer relative to said certain axis.

7. The memory cell as recited in claim 6, wherein said first interconnecting layer is disposed generally symmetrically with said second interconnecting layer relative to said certain axis.

8. The memory cell as recited in claim 2, wherein said first and second transfer transistors, said first and second driving transistors and said first and second load transistors are respectively disposed generally symmetrically in said substrate.

9. The memory cell as recited in claim 8, wherein said first and second gate electrode layers are disposed generally symmetrically in said substrate.

10. The memory cell as recited in claim 9, wherein said first and second interconnecting layers are disposed generally symmetrically in said substrate.

11. A semiconductor memory device including at least one memory cell disposed in a cell region defined on a semiconductor substrate, said cell including first and second transfer transistors, first and second driving transistors and first and second load transistors each of which has a pair of source/drain regions on opposite sides of a channel region in said substrate and a gate over the channel region, one of the source/drain regions of said first transfer transistor being connected in series with one of the source/drain regions of said first driving transistor for providing a first common region, one of the source/drain regions of said second transfer transistor being connected in series with one of the source/drain regions of said second driving transistor for providing a second common region, said first common region being connected to one of the source/drain regions of said first load transistor and to the gates of said second load transistor and said second driving transistor, said second common region being connected to one of the source/drain regions of said second load transistor and to the gates of said first load transistor and said first driving transistor, the other of the source/drain regions of each of said first and second transfer transistors being connected to a corresponding one of a pair of data lines, the improvement of said device comprising:

a first active region formed in said substrate in said cell region and extending in a first direction to provide the others of the source/drain regions of said first transfer transistor and said first driving transistor, the channel regions thereof and said first common region; and

a second active region formed spaced apart from said first active region in said substrate in said cell region and extending in said first direction to provide the others of the source/drain regions of said second transfer transistor and said second driving transistor, the channel regions thereof and said second common region.

12. The device as recited in claim 11, further comprising:

a third active region formed in said substrate in said cell region and disposed adjacent said first active region between said first and second active regions, extending in said first direction to provide the source/drain regions and the channel region of said first load transistor; and

a fourth active region formed in said substrate in said cell region and disposed adjacent said second active region between said first and second active regions, extending in said first direction to provide the source/drain regions and the channel region of said second load transistor.

13. The device as recited in claim 11, wherein said cell region is a generally rectangular-shaped region having first and second edges substantially parallel to a second direction substantially perpendicular to said first direction and third and fourth edges substantially parallel to said first direction, a first end portion of the other of the source/drain regions of said first driving transistor being contiguous to said first edge, and a second end portion of the other of the source/drain regions of said second driving transistor being contiguous to said second edge.

14. The device as recited in claim 13, further comprising:

a first bridge region formed in said substrate in said cell region and extending to said third edge adjacent said first active region along said first edge from said first end portion; and

a second bridge region formed in said substrate in said cell region and extending to said fourth edge adjacent said second active region along said second edge from said second end portion.

15. The device as recited in claim 13, further comprising a ground connection layer formed on an insulating layer over said cell region and connected to said first and second bridge regions underlying said insulating layer through contact holes.

16. The device as recited in claim 12, wherein said cell region is a generally rectangular-shaped region having first and second edges substantially parallel to a second direction substantially perpendicular to said first direction and third and fourth edges substantially parallel to said first direction, a first end portion of the other of the source/drain regions of said first driving transistor being contiguous to said first edge, a second end portion of the other of the source/drain regions of said second driving transistor being contiguous to said second edge, a third end portion of the other of the source/drain regions of said first load transistor being contiguous to said first edge, and a fourth end portion of the other of the source/drain regions of said second load transistor being contiguous to said second edge.

17. The device as recited in claim 16, further comprising:

a first bridge region formed in said substrate in said cell region and extending to said third edge adjacent said first active region along said first edge from said first end portion; and

a second bridge region formed in said substrate in said cell region and extending to said fourth edge adjacent said second active region along said second edge from said second end portion.

18. The device as recited in claim 17, further comprising:

one of a ground connection layer and a power supply connection layer formed on an insulating layer over said cell region, said ground connection layer being connected to said first and second bridge regions through contact holes in said insulating layer, said power supply connection layer being connected to said third and fourth end portions through contact holes in said insulating layer.

19. A semiconductor device including memory cells respectively formed in cell regions on a semiconductor substrate, said cell regions defined by row and column lines bounding respective ones of said cell regions, said row lines divided into alternate first and second row lines, said column lines divided into alternate first and second column lines, each of said cells including a flip-flop with cross-coupled first and second inverters, and first and second transfer transistors connected to said flip-flop, said first and second inverters respectively having first and second diffusion regions in said substrate to be connected to a ground source, said device comprising:

first bridge regions formed in said substrate such that each of said first bridge regions is interconnected through a corresponding one of intersections of said first row lines and said first column lines with said first diffusion region in each of four cell regions contiguous to said corresponding one of the intersections thereof; and

second bridge regions formed in said substrate such that each of said second bridge regions is interconnected through a corresponding one of intersections of said second row lines and said second column lines with said second diffusion region in each of four cell regions contiguous to said corresponding one of the intersections thereof;

whereby said second bridge regions crossing each of said second row lines are arranged in a staggered relationship with respect to said first bridge regions crossing each of two first row lines adjacent to said each of said second row lines.

20. The semiconductor device as recited in claim 19, wherein said first diffusion region of each cell is a source region of a first driving transistor of an n-channel type constituting said first inverter and said second diffusion region of each cell is a source region of a second driving transistor of said n-channel type constituting said second inverter.

21. The semiconductor device as recited in claim 19, wherein said first and second inverters of each cell respectively include third and fourth diffusion regions formed in said substrate to be connected to a power supply source, said third diffusion regions in said cell regions contiguous to each of said first column lines being disposed in rectilinear relationships generally parallel in a row direction on opposite sides of each of said first column lines, and said fourth diffusion regions in said cell regions contiguous to each of said second column lines being disposed in rectilinear relationships generally parallel in the row direction on opposite sides of each of said second column lines.

22. The semiconductor device as recited in claim 21, said device further comprising:

ground layers each extending in a column direction on an insulating layer over said memory cells arranged in each of alternating columns and connected to said first and second bridge regions via contact holes in said insulating layer for supplying said ground source; and

power supply layers each extending in the column direction on said insulating layer over said memory cells arranged in each column between said alternating columns and connected to said third and fourth diffusion regions via contact holes in said insulating layer for supplying said power supply source.

23. The semiconductor device as recited in claim 22, wherein said contact holes for supplying said ground source are disposed at said intersections and said contact holes for supplying said power source are disposed at portions on said first column lines intersecting with said rectilinear third diffusion regions and on said second column lines intersecting with said rectilinear fourth diffusion region.