CMOS static random access memory devices

  • US 6,147,385 A
  • Filed: 12/22/1998
  • Issued: 11/14/2000
  • Est. Priority Date: 12/23/1997
  • Status: Expired due to Term
First Claim
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1. A static random access memory cell including first and second transfer transistors of n-channel type, first and second driving transistors of the n-channel type and first and second load transistors of p-channel type, each of said transistors having source and drain regions on opposite sides of a channel region formed in a semiconductor substrate and a gate over the channel region, said cell comprising:

  • a first common region defined by the drain regions of said first transfer transistor and said first driving transistor connected in series therethrough;

    a second common region defined by the drain regions of said second transfer transistor and said second driving transistor connected in series therethrough;

    the drain region of said first load transistor disposed adjacent said first common region between said first and second common regions;

    the drain region of said second load transistor disposed between the drain region of said first load transistor and said second common region;

    first and second gate electrode layers disposed generally parallel to each other, said first gate electrode layer serving as the gates of said first driving transistor and said first load transistor and said second gate electrode layer serving as the gates of said second driving transistor and said second load transistor, each of said first and second gate electrode layers being made of a conductive material at a first level of said memory; and

    first and second interconnecting layers each made of a conductive material at a second level of said memory cell different from said first level, said first interconnecting layer connecting said first common region to the drain region of said first load transistor and to said second gate electrode layer, said second interconnecting layer connecting said second common region to the drain region of said second load transistor and to said first gate electrode layer.

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