Overvoltage-tolerant interface for integrated circuits
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1. A circuit to implement an overvoltage-tolerant integrated circuit comprising:
- a pull-up device coupled between a first supply voltage and an I/O pad; and
a body bias generator having a voltage bias node coupled to a first body electrode of the pull-up device comprising;
a first bias device coupled between the first supply voltage and the voltage bias node, wherein a control electrode of the first bias device is coupled to the I/O pad;
a second bias device coupled between the I/O pad and the voltage bias node, wherein a control electrode of the second bias device is coupled to the first supply voltage;
a first clamping device coupled between the first supply voltage and a first node, not directly connected to the voltage bias node;
a second clamping device coupled between the I/O pad and the first node; and
a third bias device to couple the first node to a control electrode of the pull-up device when the pull-up device is in a nonconducting state.
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Abstract
An input/output driver for interfacing directly with a voltage at a pad (820) which is above a supply voltage (817) for the input/output driver. This may be referred to as an "overvoltage condition. " For example, if the supply voltage is 3.3 volts, a 5-volt signal may be provided at the pad of the input/output driver. The input/output driver will tolerate this voltage level and prevent leakage current paths. This will improve the performance, reliability, and longevity of the integrated circuit. The input/output driver includes a well-bias generator (1002) for preventing leakage current paths.
75 Citations
60 Claims
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1. A circuit to implement an overvoltage-tolerant integrated circuit comprising:
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a pull-up device coupled between a first supply voltage and an I/O pad; and a body bias generator having a voltage bias node coupled to a first body electrode of the pull-up device comprising; a first bias device coupled between the first supply voltage and the voltage bias node, wherein a control electrode of the first bias device is coupled to the I/O pad; a second bias device coupled between the I/O pad and the voltage bias node, wherein a control electrode of the second bias device is coupled to the first supply voltage; a first clamping device coupled between the first supply voltage and a first node, not directly connected to the voltage bias node; a second clamping device coupled between the I/O pad and the first node; and a third bias device to couple the first node to a control electrode of the pull-up device when the pull-up device is in a nonconducting state. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8)
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9. An integrated circuit comprising:
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a pull-up device coupled between a first supply voltage and an I/O pad; and a body bias generator having a voltage bias node coupled to a first body electrode of the pull-up device comprising; a first bias device coupled between the first supply voltage and the voltage bias node, wherein a control electrode of the first bias device is coupled to the I/O pad; a second bias device coupled between the I/O pad and the voltage bias node, wherein a control electrode of the second bias device is coupled to the first supply voltage; a first clamping device coupled between the first supply voltage and a first node; a second clamping device coupled between the I/O pad and the first node; a third bias device to couple the first node to a control electrode of the pull-up device when the pull-up device is in a nonconducting state; and a voltage clamp device coupled to clamp the voltage bias node to about a voltage level at the I/O pad.
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10. A circuit to implement an overvoltage-tolerant integrated circuit comprising:
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a pull-up device coupled between a first supply voltage and an I/O pad; and a body bias generator having a voltage bias node coupled to a first body electrode of the pull-up device comprising; a first bias device coupled between the first supply voltage and the voltage bias node, wherein a control electrode of the first bias device is coupled to the I/O pad; a second bias device coupled between the I/O pad and the voltage bias node, wherein a control electrode of the second bias device is coupled to the first supply voltage; and
;a third bias device to couple the voltage bias node to a control electrode of the pull-up device whenever the pull-up device is in a nonconducting state. - View Dependent Claims (11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23)
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24. An intergrated circuit comprising:
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a pull-up device coupled between a first supply voltage and an I/O pad; a predriver to drive the pull-up device; and an isolation device between the predriver and the control electrode of the pull-up device, wherein the isolation device is a pass transistor having a control electrode coupled to the first supply voltage; and a body bias generator having a voltage bias node coupled to a first body electrode of the pull-up device comprising; a first bias device coupled between the first supply voltage and the voltage bias node, wherein a control electrode of the first bias device is coupled to the I/O pad; a second bias device coupled between the I/O pad and the voltage bias node, wherein a control electrode of the second bias device is coupled to the first supply voltage; a first clamping device coupled between the first supply voltage and a first node; a second clamping device coupled between the I/O pad and the first node; and a third bias device to couple the first node to a control electrode of the pull-up device when the pull-up device is in a nonconducting state.
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25. An integrated circuit comprising:
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a pull-up device coupled between a first supply voltage and an I/O pad; a first pass device coupled between the I/O pad and the control electrode of the pull-up device, wherein a control electrode of the first pass device is coupled to the first supply voltage; and a body bias generator having a voltage bias node coupled to a first body electrode of the pull-up device comprising; a first bias device coupled between the first supply voltage and the voltage bias node, wherein a control electrode of the first bias device is coupled to the I/O pad; a second bias device coupled between the I/O pad and the voltage bias node, wherein a control electrode of the second bias device is coupled to the first supply voltage; a first clamping device coupled between the first supply voltage and a first node; a second clamping device coupled between the I/O pad and the first node; and a third bias device to couple the first node to a control electrode of the pull-up device when the pull-up device is in a nonconducting state. - View Dependent Claims (26, 27, 28)
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29. A circuit to implement an overvoltage-tolerant integrated circuit comprising:
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a pull-up device coupled between a first supply voltage and an I/O pad; a predriver to drive the pull-up device; and an isolation device between the predriver and the control electrode of the pull-up device, wherein the isolation device is a pass transistor having a control electrode coupled to the first supply voltage, and a body bias generator having a voltage bias node coupled to a first body electrode of the pull-up device comprising; a first bias device coupled between the first supply voltage and the voltage bias node, wherein a control electrode of the first bias device is coupled to the I/O pad; and a second bias device coupled between the I/O pad and the voltage bias node, wherein a control electrode of the second bias device is coupled to the first supply voltage, wherein the first bias device and the second bias device have a first gate oxide thickness that is thicker than a second gate oxide thickness of transistors used to implement the predriver. - View Dependent Claims (30, 31, 32, 33, 34, 35, 36, 37, 38, 39, 40, 41, 42, 43, 44, 45, 46, 47)
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48. A circuit to implement an overvoltage-tolerant integrated circuit comprising:
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a pull-up device coupled between a first supply voltage and an I/O pad; a predriver to drive a control electrode of the pull-up device with a pull-up signal; and a body bias generator, having a voltage bias node coupled to a first body electrode of the pull-up device, comprising; a first bias device coupled between the first supply voltage and the voltage bias node, wherein a control electrode of the first bias device is coupled to the I/O pad; a second bias device coupled between the I/O pad and the voltage bias node, wherein a control electrode of the second bias device is coupled to the first supply voltage; and a third bias device, coupled between the voltage bias node and the control electrode of the pull-up device, wherein a control electrode of the third bias device is coupled to an inverted version of the pull-up signal. - View Dependent Claims (49, 50, 51, 52, 53, 54, 55, 56, 57, 58, 59, 60)
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Specification