Method of invoking a power-down mode on an integrated circuit by monitoring a normally changing input signal

• US 6,147,528 A
• Filed: 03/13/1998
• Issued: 11/14/2000
• Est. Priority Date: 03/13/1998
• Status: Expired due to Term

• Current Assignee: Analog Devices, Inc.
• Original Assignee: Analog Devices, Inc.
• Inventors: O'Dowd, John, Wynne, John
• Primary Examiner(s): Zweizig, Jeffrey
• Application Number:
  US09/041,937
• Time in Patent Office: 977 Days
• Field of Search: 327/18, 327/20, 327/142, 327/143, 327/165, 327/198
• US Class Current: 327/142
• CPC Class Codes: G06F 1/24 Resetting means
• CPC Class Codes: G06F 1/3203 Power management, i.e. event-based initiation of a power-saving mode
• CPC Class Codes: G06F 1/3287 by switching off individual functional units in the computer system
• CPC Class Codes: Y02D 10/00 Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

An integrated circuit comprises means responsive to a normally changing signal at an input of the integrated circuit to implement a primary function of the circuit, and means for monitoring this normally changing signal at the input in question of the integrated circuit. This monitoring means is responsive to suspension of the normally changing signal to communicate a signal for implementation of a secondary function of the circuit. In an exemplary embodiment, the invention is directed towards implementation of power-down of the circuit, without using an explicit power-down or reset pin. An input signal which normally changes at minimum rate, e.g. preferably a clock signal, is held in a fixed state for a minimum duration to invoke the reset or power-down mode. An integrated circuit may thus be powered-down or reset where no explicit power-down or reset pin is available.

Claims

1. An integrated circuit having a plurality of pins, to at least one of which a functional input signal is applied, and to another of which a normally repeating signal is applied:

wherein normal operation of the circuit is implemented in the presence of said normally repeating signal at said another of said plurality of pins, and a reduced power consumption mode of operation of the circuit is implemented by suspension of said normally repeating signal.

2. The integrated circuit of claim 1, wherein implementation of said reduced power consumption mode of operation is terminated by resumption of said normally repeating signal.

3. The integrated circuit of claim 1, wherein the presence of said normally repeating signal is monitored by a self-contained timing circuit.

4. The integrated circuit of claim 1, wherein implementation of said normal operation is terminated by suspension of said normally repeating signal.

5. The integrated circuit of claim 1, wherein said another of said plurality of pins is a clock pin of the integrated circuit and said normally repeating signal comprises a clock signal applied to said clock pin.

6. An integrated circuit having a plurality of pins, to at least one of which a functional input signal is applied, and to another of which a normally repeating signal is applied, normal operation of the circuit being implemented in the presence of said normally repeating signal, and a reduced power consumption mode of operation being implemented by suspension of said normally repeating signal,

wherein,

(1) said reduced power consumption mode of operation is terminated by resumption of said normally repeating signal,

(2) said another of said plurality of pins is a clock pin of the integrated circuit, and

(3) said normally repeating signal comprises a clock signal applied to said clock pin.

7. An integrated circuit comprising:

(a) means responsive to a signal applied to a first input of the integrated circuit to effect a required circuit operation,

(b) means responsive to a normally changing signal applied to a second input of the integrated circuit to enable implementation of normal operation of the circuit, and

(c) means for monitoring said normally changing signal at said second input of the integrated circuit, said monitoring means being responsive to suspension of said normally changing signal to communicate a signal for implementation of a reduced power consumption mode of operation of the circuit.

8. The integrated circuit of claim 7, wherein said monitoring means is responsive to resumption of said normally changing signal at said second input of the integrated circuit to terminate implementation of said reduced power consumption mode of operation.

9. The integrated circuit of claim 7, wherein said monitoring means comprises a self-contained timing circuit.

10. The integrated circuit of claim 7, wherein said means responsive to said normally changing signal is responsive to termination of said normally changing signal to terminate implementation of said normal operation.

11. The integrated circuit of claim 7, wherein said another of said plurality of pins is a clock pin of the integrated circuit and said normally changing signal comprises a clock signal applied to said clock pin.

12. An integrated circuit comprising:

(a) means responsive to a signal applied to a first input of the integrated circuit to effect a required circuit operation,

(b) means responsive to a normally changing signal applied a second input of the integrated circuit to enable implementation of normal operation of the circuit, and

(c) means responsive to suspension of said normally changing signal to enable implementation of a reduced power consumption mode of operation.

13. The integrated circuit of claim 12, wherein said means responsive to suspension of said normally changing signal is further responsive to resumption of said normally changing signal to terminate implementation of said reduced power consumption mode of operation.

14. The integrated circuit of claim 12, comprising a self-contained timing circuit for monitoring the presence of said normally changing signal.

15. The integrated circuit of claim 12, wherein said means responsive to said normally changing signal to enable implementation of said normal operation is responsive to suspension of said normally changing signal to terminate implementation of said normal operation.

16. The integrated circuit of claim 12, wherein said second input of the integrated circuit is a clock pin and said normally changing signal comprises a clock signal applied to said clock pin.

17. An integrated circuit comprising:

(a) means responsive to a signal applied to a first input of the integrated circuit to effect a required circuit operation,

(b) means responsive to a normally changing signal applied to a second input of the integrated circuit to enable implementation of normal operation of the circuit, and

(c) means responsive to suspension of said normally changing signal to enable implementation of a reduced power consumption mode of operation of the circuit,

wherein

(i) said means responsive to suspension of said normally changing signal is further responsive to resumption of said normally changing signal to terminate implementation of said reduced power consumption mode of operation,

(ii) said second input of the integrated circuit is a clock pin, and

(iii) said normally changing signal comprises a clock signal applied to said clock pin.

18. A method of implementing a reduced power consumption mode of operation of an integrated circuit having a plurality of pins, to at least one of which a functional input signal is applied and to another of which a normally repeating signal is applied, the method comprising the steps of:

(a) monitoring the presence of said normally repeating signal at said another of said plurality of pins,

(b) implementing normal operation of the circuit in the presence of said normally repeating signal,

(c) implementing a reduced power consumption mode of operation of the circuit in the absence of said normally repeating signal, and

(d) terminating the implementation of said reduced power consumption mode of operation on resumption of said normally repeating signal.

19. A method according to claim 18, wherein a period of absence of said normally repeating signal is established by holding said another of said plurality of pins in a logic low state.

20. A method according to claim 18, wherein said normally repeating signal is a clock signal and a period of absence of said clock signal is established by holding said another of said plurality of pins in a logic low state for a duration longer than the normal clock low interval.